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decaWave DW1000 User Manual

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DW1000 USER MANUAL
DW1000 USER MANUAL
HOW TO USE, CONFIGURE AND
PROGRAM THE DW1000 UWB
TRANSCEIVER
This document is subject to change without notice
© Decawave Ltd 2017
Version 2.12
Page 1 of 242

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Summary of Contents for decaWave DW1000

  • Page 1 DW1000 USER MANUAL DW1000 USER MANUAL HOW TO USE, CONFIGURE AND PROGRAM THE DW1000 UWB TRANSCEIVER This document is subject to change without notice © Decawave Ltd 2017 Version 2.12 Page 1 of 242...

  • Page 2: Table Of Contents

    UTOMATIC CKNOWLEDGEMENT 12.3 ....224 OUBLE SIDED ANGING RANSMIT AND AUTOMATICALLY WAIT FOR RESPONSE APPENDIX 4: ABBREVIATIONS AND ACRONYMS OTHER FEATURES OF THE DW1000 ....55 APPENDIX 5: REFERENCES ......233 ......55 XTERNAL YNCHRONISATION ....58 XTERNAL OWER MPLIFICATION DOCUMENT HISTORY ........

  • Page 3: List Of Figures

    DW1000 User Manual List of Figures 1: SPI R ....11 21: P SNIFF IGURE EAD AND RITE RANSACTIONS IGURE OWER PROFILE FOR OW DUTY CYCLE WHERE 2: S ......... 44 IGURE INGLE OCTET HEADER OF THE NON INDEXED A FRAME IS NOT RECEIVED ............

  • Page 4: List Of Tables

    DW1000 User Manual List of Tables 1: M DW1000 ..16 28: R 26 – GPIO ABLE OPERATIONAL STATES MODES ABLE EGISTER FILE CONTROL AND STATUS 2: M DW1000 D ............128 ABLE XCERPT FROM HEET OVERVIEW ........20 29: R 27 –...
  • Page 5 DW1000 User Manual 57: R ....207 ABLE ECOMMENDED PREAMBLE LENGTHS 58: T ALOHA ..208 ABLE RANSMISSIONS PER SECOND USING 59: T ..210 ABLE ECHNIQUES TO SAVE POWER IN RECEIVING 60: P ........214 ABLE REAMBLE PARAMETERS 61: DW1000...
  • Page 6 Decawave customers using or selling Decawave products in such a manner do so entirely at their own risk and agree to fully indemnify Decawave and its representatives against any damages arising out of the use of Decawave products in such safety-critical applications.

  • Page 7: Introduction

    Information already contained in the DW1000 data sheet is not reproduced here and it is intended that the reader should use this user manual in conjunction with the DW1000 data sheet.
  • Page 8 API functions to initialise, configure and control the DW1000. It provides API functions for transmission and reception, and for driving the functionalities of the IC. The DW1000 driver source code is targeted for the ARM cortex M3 but is readily portable to other microprocessor systems. The code comes with a number of demo/test applications, (including a two-way ranging application), to exercise the API and the features of the DW1000.
  • Page 9 DW1000 User Manual Data Rate Where a data rate of 6.8 Mbps is referred to, this is equivalent to the 6.81/6.8 Mbps data rate in [1]. © Decawave Ltd 2017 Version 2.12 Page 9 of 242...

  • Page 10: Overview Of The Dw1000

    DW1000.The SPI bus signals, their voltage levels and signal timings are described in the DW1000 data sheet. The host system reads and writes DW1000 registers via the SPI. This section describes the format of the SPI transactions. For details of the SPI physical circuits, operational mode configuration and timing parameters please refer to the DW1000 data sheet.

  • Page 11: Figure 1: Spi Read And Writet

    DW1000 User Manual by the DW1000, and for a write transaction all octets output by the DW1000 should be ignored by the host system. Read Transaction Header ignored by DW 1000 MOSI Host should ignore Transaction Body – read data output by DW 1000...

  • Page 12: Figure 2: Single Octet Header Of The Non

    1 indicating that a sub-index is present. The register (file) ID in the first octet selects the top level address of the DW1000 parameter block being accessed. In the second octet bit-7 is zero indicating that a further transaction header octet is not present and that the remaining 7 bits of octet-2 are a short sub-index into the register file.

  • Page 13: Figure 5: Example Short-Indexed Read Of 3

    1 indicating that a sub-index is present. The register (file) ID in the first octet selects the top level addressing of the DW1000 parameter or parameter block being accessed. In the second transaction header octet bit-7 is set indicating the long form of indexed addressing is to be employed and thus the remaining seven bits of the second octet along with all of the third transaction header octet form a 15-bit sub-index into the selected register file.
  • Page 14 2.2.2 Interrupts The DW1000 can be configured to assert its IRQ pin on the occurrence of one or more status events. The assertion of the IRQ pin can be used to interrupt the host controller and redirect program flow to deal with the cause of the event.

  • Page 15: Figure 8: Dw1000 State Diagram

    RX complete? TX complete? Snooze set? AUTO SLEEP? SNOOZE IRQ Pending? Store selected AON configuration Snooze count complete? SLEEP or DEEPSLEEP? SLEEP DEEPSLEEP Wakeup Event? Figure 8: DW1000 State Diagram © Decawave Ltd 2017 Version 2.12 Page 15 of 242...

  • Page 16: Table 1: Main Dw1000

    DW1000 is fed from this 19.2 MHz XTI clock. If the DW1000 has entered INIT state from a SLEEP or DEEPSLEEP state, (or as a result of a reset), then the register configurations can be automatically restored from the AON memory array.
  • Page 17 DW1000 will enter the SLEEP or DEEPSLEEP state automatically, (as long as no host interrupts are pending). Note that it is not possible to be in the TX and RX states simultaneously – the DW1000 is a half-duplex transceiver device.

  • Page 18: Power O N Reset

    DW1000 IC. In this SLEEP state the power drain is < 1 µA. The DW1000 may wake from SLEEP state when the sleep timer elapses.
  • Page 19 2.4.1.2 Configuration register preservation Prior to entering the SLEEP and DEEPSLEEP states and prior to exiting the WAKEUP state, the main DW1000 configurations are copied to and from an Always-On memory (AON). Power is maintained to AON memory at all times, even in SLEEP and DEEPSLEEP states.

  • Page 20: Default Configuration On

    5, preamble code 4 and mode 2. Channel numbers and preamble codes are as specified in the standard, IEEE 802.15.4-2011 [1] and mode 2 is as specified in the DW1000 data sheet modes and comprises the following configurations:...

  • Page 21: Table 3: Gpio Default Functions

    DW1000 User Manual GPIOs are set to mode 0, their default function as shown in Table 3. Table 3: GPIO Default Functions GPIO Pin Default Function GPIO0/RXOKLED GPIO0 GPIO1/SFDLED GPIO1 GPIO2/RXLED GPIO2 GPIO3/TXLED GPIO3 GPIO4/EXTPA GPIO4 GPIO5/EXTTXE/SPIPHA GPIO5 GPIO6/EXTRXE/SPIPOL GPIO6...

  • Page 22: Table 23: Register File

    DW1000 initialisation (because after powering up the DW1000 (or after exiting SLEEP or DEEPSLEEP states) the LDE RAM is empty). This should be done before the receiver is enabled if it is important to timestamp this received frame. If the LDE code is not...
  • Page 23 2.5.5.10 LDELOAD LDELOAD is reset to 0 by default. This needs to be set as part of DW1000 initialisation and before receiver enable, if it is important to get timestamp and diagnostic information from received frames. See description LDELOAD bit for further information. The table below outlines the programming steps to load the microcode from ROM into RAM.

  • Page 24: Table 4: Register Accesses Required To Load

    DW1000 User Manual Table 4: Register accesses required to load LDE microcode Data Step Register Data Instruction Length Number Address (Write/Read) (Bytes) Write Sub-Register 0x36:00 (PMSC_CTRL0) 0x0301 Write Sub-Register 0x2D:06 (OTP_CTRL) 0x8000 Wait 150 µs Write Sub-Register 0x36:00 (PMSC_CTRL0) 0x0200 2.5.5.11...

  • Page 25: Message Transmission

    DW1000 User Manual Message Transmission Basic Transmission The transmission of data frames is one of the basic functions of the DW1000 transceiver. Figure 10 shows the elements of the transmitted frame. Preamble SFD PHR Data 21 bits IEEE STD : Up to 127 coded octets...

  • Page 26: Transmission Timestamp

    (defined as the RMARKER) is the event nominated as the transmit time-stamp. The DW1000 digital transmit circuitry takes note of the system clock counter as the RAW transmit timestamp at the point when it begins sending the PHR. It then adds to this the transmit antenna delay (configured in Register file: 0x18 –...

  • Page 27: Frame

    Extended Length Data Frames Standard IEEE 802.15.4-2011 UWB frames carry up to 127 bytes of payload. The DW1000 supports a non- standard mode of operation with frame lengths up to 1023 bytes of data. This mode of operation is enabled via the PHR_MODE selection bits of Register file: 0x04 –...

  • Page 28: Table 5: Preamble Duration Field Values In

    DW1000 User Manual operating with standard frame encoding because the SECDED error check sequence of the PHR in long frame mode is incompatible with the standard encoding. Note also that the probability of an error occurring within a frame increases as the frame length is increased, and as a result of this increasing the frame length may or may not improve system throughput depending on the frame error rate and the need to retransmit frames when there is an error.

  • Page 29: High Speed Transmission

    Control. So preamble transmission can begin before the TX data is written into the DW1000. The host microprocessor then has the time of any fixed response delay, and the time for sending preamble and SFD before it needs to have the frame length set in TFLEN and TFLE ready for the ©...
  • Page 30 513 and 1023 octets. Similarly if DW1000 is actively receiving, data may be written to the TX_BUFFER while the receiver is active. The following are the points of note for optimum throughput or fast response turnaround:...
  • Page 31 If the host system has not been quick enough in writing the data this will result in the frame being sent with the wrong data but with a bad CRC also. The DW1000 transmitter includes a circuit to detect the host microprocessor writing to the buffer between the selected TXBOFFS and any address the IC has already consumed the data from, which is taken to mean that the data is being written too late for transmission.

  • Page 32: Message Reception

    DW1000 User Manual Message Reception Basic Reception The reception of a frame is enabled by a host request or by an automatic re-enabling of the receiver. The receiver will search for preamble continually until preamble has been detected or acquired, when a demodulation will be attempted.
  • Page 33 SFD or the long 64-symbol SFD. This is done via the RXM110K configuration bit in Register file: 0x04 – System Configuration. The DW1000 also has the capability of programming non-standard SFD sequences that give improved performance, see Register file: 0x21 – User defined SFD sequence.
  • Page 34 RMARKER arrives at the antenna as the significant event that is time-stamped. The DW1000 digital receiver circuitry takes a coarse timestamp of the symbol in which the RMARKER event occurs and adds a various correction factors to give a resultant adjusted time stamp value, which is the time at which the RMARKER arrived at the antenna.

  • Page 35: Delayed Receive

    Double Receive Buffer This DW1000 has a pair of receive buffers offering the capability to receive into one of the pair while the host system is reading previously received data from the other buffer of the pair. This is useful in a TDOA RTLS anchor node where it is desired to have the receiver on as much as possible to avoid missing any tag blink messages.

  • Page 36: Table 7: Registers In The Rx Double

    All of 4.3.1 Enabling double-buffered operation By default the DW1000 operates in a single buffered mode that is appropriate for many applications. When using double-buffered mode it is appropriate to also configure the DW1000 to automatically re-enable the receiver (moving on to the other buffer of the swinging set) as soon as it has completed receiving any previous frame.
  • Page 37 DW1000 User Manual Status Register). Reception of a new frame with good CRC will cause the ICRBP bit to increment (or toggle). In the case that a received frame is rejected by frame filtering or bad CRC the ICRBP will not move on and the buffer will be reused for the next incoming frame.

  • Page 38: Figure 14: Flow Chart For Using Double

    DW1000 User Manual Set up RX channel and other parameters as required Set DIS_DRXB bit = 0 in reg:04 to Enable double buffering Set RXAUTR bit = 1 in reg:04 to enable RX auto-re-enable Read SYS_STATUS reg:0F to checking that HSRBP == ICRBP...

  • Page 39: Low-Power Listening

    Low-Power Listening Low-power listening is a feature whereby the DW1000 is predominantly in the SLEEP state but wakes periodically for a very short time to sample the air for a preamble sequence. If no preamble is seen the DW1000 automatically returns to SLEEP for another period, however if preamble is seen the DW1000 does ©...

  • Page 40: Figure 16: Low Power Listening With Two Sleep Times

    To avoid this, and give a better performing wakeup, the DW1000 includes the ability to do a two-phase listen. This has a long sleep period followed by a sampling of the air, followed by a short sleep period and then another sampling of the air. The short sleep time period is set to ensure that if the first listen hits a message (missing the preamble) then the next listen will see preamble.

  • Page 41: Low-Power Sniff Mode

    When a frame is received, low-power listening must be deactivated by clearing the ARXSLP bit before the RXFCG interrupt is cleared. This is required to ensure that the DW1000 does not go back to sleep as soon as the interrupt is cleared, which would prevent the user from reading the frame data correctly. Once the received frame has been handled, low-power listening mode can be reactivated by setting the ARXSLP bit once more and putting the DW1000 back into reception or sleep mode.

  • Page 42: Figure 18: State Transitions During

    Figure 18: State transitions during SNIFF mode 4.5.1 SNIFF mode In SNIFF mode the DW1000 alternates between the RX (on) and the IDLE (off) states. To enable SNIFF mode two parameters SNIFF_ONT (sniff on time) and SNIFF_OFFT (the off time) need to be configured in Register file: 0x1D –...

  • Page 43: Figure 19: Power Profile For Sniff

    4.5.2 Low duty-cycle SNIFF mode In Low duty-cycle SNIFF mode, where the off time is larger, the DW1000 can be configured to spend this off time in the INIT state which is lower power than the IDLE state (used for the off period of a SNIFF). This is enabled by setting the ARX2INIT bit in Sub-Register 0x36:04 –...

  • Page 44: Diagnostics

    The power saving of Low duty-cycle SNIFF mode is only realised when the off period is greater than 1 (i.e. > 6.6 µs). This is because after the timer expiry the DW1000 will enter the IDLE state as the PLL is turned on and locks (this takes approximately 5 µs) before progressing into the RX state.
  • Page 45 RX timestamp information might be used to select which anchors’ RX message timestamps to feed into the location engine. The following details the elements of receive status reported by the DW1000 that may be used to assess the quality of a received message and any related timestamp.
  • Page 46 DW1000 User Manual 4.7.1 Estimating the signal power in the first path An estimate of the power in the first path signal may be calculated (in dBm) using the formula: Where: F1 = the First Path Amplitude (point 1) magnitude value reported in the FP_AMPL1 field of Register file: 0x15 –...

  • Page 47: Figure 22: Estimated Rx

    DW1000 User Manual Estimated RX LEVEL (16MHz PRF Free Space) Estimated RX LEVEL (64MHz PRF Free Space) Estimated RX LEVEL (64MHz PRF Multipath) Actual RX LEVEL Estimated RX LEVEL (dBm) -100 -105 -105 -100 Actual RX LEVEL (dBm) Figure 22: Estimated RX level versus actual RX level ©...

  • Page 48: Media Access Control (Mac) Hardware Features

    Frame filtering Frame filtering is a feature of the DW1000 IC that can parse the received data of a frame that complies with the MAC encoding defined in the IEEE 802.15.4–2011 standard, identifying the frame type and its destination address fields, match these against the IC’s own address information, and only accept frames that pass the filtering rules.
  • Page 49 DW1000 User Manual  The frame type must be allowed for reception: o The FFAB configuration bit must be set to allow a Beacon frame to be received. o The FFAD configuration bit must be set to allow a Data frame to be received.
  • Page 50 The preamble length of the frame requesting acknowledgement (ACK) is encoded in the PHR of that frame, (see section 10.4 – PHY header), and decoded in the DW1000 receiver (and reported in the RXPSR field of Register file: 0x10 – RX Frame Information Register).

  • Page 51: Table 8: Auto -Ack

    Greater than 2048 4096 NOTE *: These (asterisked) short preamble lengths will not be received by the DW1000. Use cases where this is likely to occur frequently should be avoided by one of the following strategies: (a) using a longer preamble for retransmission when no ACK is received, (b) not using the extended length frames mode, or, (c) by using the host microprocessor to generate the ACK in place of the DW1000’s auto-ACK feature.
  • Page 52 TRXOFF set at the same time. No signal will actually be transmitted as a result of this operation. This operation should be performed each time the communication parameters are configured or reconfigured as this can change the SFD sequence the DW1000 will use for the next transmission. 5.3.2 Automatic Receiver Re-Enable...

  • Page 53: Transmit And Automatically Wait For Response

    DW1000 User Manual Please refer to the standard [1] for details of this. The DW1000 does not automatically determine the frame pending bit inserted into the automatically-generated ACK frames. Instead it copies the value of the AACKPEND configuration bit (from Register file: 0x04 –...
  • Page 54 DW1000 User Manual frame to be overwritten, or other behaviour such as receiver timeouts resulting from the device being in the RX state rather than in IDLE. © Decawave Ltd 2017 Version 2.12 Page 54 of 242...

  • Page 55: Other Features Of The Dw1000

    EXTCLK pin. The SYNC input pin is sampled on the rising edge of EXTCLK. Refer to the DW1000 datasheet for setup and hold times of the SYNC pin. The SYNC input provides a common reference point in time to synchronise the DW1000 with the accuracy necessary to achieve high resolution location estimation.

  • Page 56: Decawave Ltd

    DW1000 User Manual To configure DW1000 for OSTR mode, the OSTRM bit in the EC_CTRL register is set and the WAIT value is set to the desired delay value. When a counter running on the 38.4 MHz external clock and initiated on the rising edge of the SYNC signal equals the WAIT programmed value, the DW1000 timebase counter will be reset.

  • Page 57: Figure 24: Synchronised Transmission

    This allows a user to have a timebase outside the DW1000, and to receive timing information about the receive events in this timebase. OSRS mode is configured by setting the OSRSM bit in the EC_CTRL register, see Register file: 0x24 –...

  • Page 58: External Powera

    DW1000 it is necessary to employ external amplification of the transmitted signal. The DW1000 provides signals (using the GPIO lines in a special mode) to control the turn-on of the power amplifier and to control the analog switching of the transmitter and receiver signal paths appropriately. This...

  • Page 59: Table 10: Otp Memory Map

    DW1000 User Manual 6.3.1 OTP memory map The OTP memory locations are as defined in Table 10. The OTP memory locations are each 32-bits wide, OTP addresses are word addresses so each increment of address specifies a different 32-bit word.

  • Page 60: Table 11: Otp_Srdat R

    DW1000 User Manual The SR (“Special Register”) is a 32-bit segment of OTP that is directly readable via the register interface upon power up. To programme the SR register follow the normal OTP programming method but set the OTP address to 0x400. The value of the SR register can be directly read back at address Register file: 0x2D –...

  • Page 61: Measuring Ic

    Measuring IC temperature and voltage The DW1000 is equipped with a low speed 8-bit SAR A/D convertor which can be configured to sample values from an internal IC temperature sensor and also from a battery voltage monitor on the VDDAON ©...

  • Page 62: Table 14: A N Example Of Register Accesses To Perform A

    These readings can be manually run under host control, or they can be configured to be run automatically each time the DW1000 enters the WAKEUP state. This automatic mode allows the temperature and voltage to be read while the device is in a low power state, which will give the ambient temperature and unloaded battery voltage.

  • Page 63: The Dw1000 Register Set

    Section 7.2 gives a detailed description of each register. Note: When writing to any of the DW1000 registers care must be taken not to write beyond the published length of the selected register and not to write to any of the reserved register locations. Doing so may cause the device to malfunction.

  • Page 64: Id (Octets)

    DW1000 User Manual Length Type Mnemonic Description (octets) 0x15 RX_TIME Receive Message Time of Arrival (in double buffer set) 0x16 Reserved 0x17 TX_TIME Transmit Message Time of Sending 0x18 TX_ANTD 16-bit Delay from Transmit to Antenna 0x19 SYS_STATE System State information...

  • Page 65: Detailed Register Description

    Detailed register description 7.2.1 Terminology Section 7.1 gives an overview of the DW1000 register set presenting all top level register file ID addresses in Table 15. This section describes in detail the contents and functionality of these register files in separate sub sections.
  • Page 66 The value is 0xDECA in hex. reg:00:00 bits:31–16 For the production DW1000 the Device ID is set to 0xDECA0130. The register descriptions in this user manual relate to that DW1000 device and are not valid for any earlier sample parts. © Decawave Ltd 2017 Version 2.12...

  • Page 67: 0X01 8 Rw Eui

    Certain IEEE 802.15.4 defined frames use a 64-bit source address. The software (MAC) generating such frames is expected to insert the EUI within the frame before the frame is written to the DW1000’s transmit buffer.

  • Page 68: 0X03 4 Rw Panadr

    0x03 contains two 16-bit parameters, the PAN Identifier and the Short Address. When the DW1000 is powered-up or reset both the PAN Identifier and the Short Address in this register are reset to the value 0xFFFF. The host software (MAC) should program the appropriate values into this register if it wishes to use the DW1000’s receive frame filtering or automatic acknowledgement generation...

  • Page 69: 0X04 4 Rw Sys_Cfg

    DW1000 User Manual The host software (MAC) only needs to program this register if it is using the DW1000’s receive frame filtering and automatic acknowledgement generation functions. The sub-fields are: Field Description of fields within Register file: 0x03 – PAN Identifier and Short Address SHORT_ADDR Short Address.
  • Page 70 (if present) must match the node’s own address or the frame will not be accepted. When FFBC is set to 1 the DW1000 will behave as a coordinator. When FFBC is clear the DW1000 will behave as an ordinary normal node.
  • Page 71 SPI_EDGE SPI data launch edge. This bit allows the system integrator the ability to control the launch edge used for SPI data from the DW1000 on the MISO SPI data output line. This may be reg:04:00 used to select the MISO output operation most suitable to the target system. When bit:10 SPI_EDGE is 0 the DW1000 uses the sampling edge to launch MISO data.
  • Page 72 DW1000 User Manual Field Description of fields within Register file: 0x04 – System Configuration DIS_RSDE Disable Receiver Abort on RSD error. During normal reception (i.e. with the DIS_RSDE bit cleared to its recommended default zero value) when the Reed Solomon decoder detects...
  • Page 73 Reserved – this register file is reserved Register map register file 0x05 is reserved for future use. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. © Decawave Ltd 2017 Version 2.12...

  • Page 74: Ro Sys_Time

    64 GHz, or more precisely 499.2 MHz × 128 which is 63.8976 GHz. In line with this when the DW1000 is in idle mode with the digital PLL enabled, the System Time Counter is incremented at a rate of 125 MHz in units of 512.
  • Page 75 850 kbps 6.8 Mbps reserved Transmit Ranging enable. This bit has no operational effect on the DW1000; however it is copied into the ranging bit in the PHY header (PHR) of the transmitted frame, identifying the reg:08:00 frame as a ranging frame. In some receiver implementations this may be used to enable bit: 15 hardware or software associated with time-stamping the frame.

  • Page 76: Table 16: Preamble Length Selection

    There are four standard preamble lengths are defined for the 802.15.4 UWB PHY – these are 16, 64, 1024 and 4096 symbols. The DW1000 has facility via the PE (Preamble Extension) configuration to send preambles of additional (non-standard) intermediary lengths. Table 16 below lists the selectable preamble lengths.

  • Page 77: 0X09 1024 Wo Tx_Buffer

    Where the transmitter is enabled to begin a new frame the DW1000 makes sure that IFSDELAY symbol times have passed. A new value of IFSDELAY for the next frame should not be set until after the end-of-frame...

  • Page 78: Rw Rx_Fwto

    DW1000 when either a frame is received or the programmed timeout has elapsed. While many microcontrollers have timers that might be used for this purpose, including this RX timeout functionality in the DW1000 allows additional flexibility to the system designer in selecting the microprocessor to optimise the solution.

  • Page 79: Srw Sys_Ctrl

    Note: The frame wait timeout may also be employed with double buffering, where after a frame is received the DW1000 automatically re-enables the receiver (moving on to potentially receive a new frame in the next buffer). Here when RXWTOE is set the countdown will be restarted as the receiver re-enables to receive into the next buffer.
  • Page 80 IEEE 802.15.4 frame protocol is being employed, and can also be of use to induce a FCS error in the remote receiver during testing. The SFCST bit will clear as soon as the DW1000 sees TXSTRT and initiates transmission.
  • Page 81 DW1000 sees and acts on it. TRXOFF Transceiver Off. When this is set the DW1000 returns to idle mode immediately. Any TX or RX activity that is in progress at that time will be aborted. The TRXOFF bit will clear as soon as the reg:0D:00 DW1000 sees it and returns the IC to idle mode.

  • Page 82: Rw Sys_Mask

    RXDLYE and RXENAB should be set to correctly invoke the delayed receiving feature. The DW1000 then precisely controls the RX turn on time so that it is ready to receive the first symbol of preamble at the specified DX_TIME start time. In cases when the received time can...
  • Page 83 DW1000 User Manual REG:0E:00 – SYS_MASK – System Event Mask 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 84 DW1000 User Manual Field Description of fields within Register file: 0x0E – System Event Mask Register MRXPHD Mask receiver PHY header detect event. When MRXPHD is 0 the RXPHD event status bit will not generate an interrupt. When MRXPHD is 1 and the RXPHD event status bit is 1, the reg:0E:00 hardware IRQ interrupt line will be asserted to generate an interrupt.

  • Page 85: 0X0F Srw Sys_Status

    DW1000 User Manual Field Description of fields within Register file: 0x0E – System Event Mask Register MRXSFDTO Mask Receive timeout event. When MRXSFDTO is 0 the RXSFDTO event status bit will not generate an interrupt. When MRXSFDTO is 1 and the RXSFDTO event status bit is 1, the reg:0E:00 hardware IRQ interrupt line will be asserted to generate an interrupt.
  • Page 86 CPLOCK Clock PLL Lock. The CPLOCK event status bit indicates that the digital clock PLL has locked. This may be used as an interrupt to indicate that the DW1000 clock is operating at full speed, reg:0F:00 after which the SPI can be run at its maximum rate also. The CPLOCK bit is cleared by writing a bit:1 1 to it.
  • Page 87 PHR, which also marks the RMARKER whose arrival at the antenna is the event that defines the frame arrival timestamp. To accurately determine this timestamp the DW1000 employs an internal algorithm to adjust the RMARKER receive time. Among other functions this performs a leading edge detection search on the channel impulse response and subtracts the receive antenna delay as programmed in Sub-Register 0x2E:1804 –...
  • Page 88 DW1000 User Manual Field Description of fields within Register file: 0x0F – System Event Status Register RXPHE Receiver PHY Header Error. This event status bit is set to indicate that the receiver has found a non-correctable error in the PHR. The PHR includes a SECDED error check sequence (see reg:0F:00 section 10.4) that can correct a single bit error and detect a double bit error.
  • Page 89 (60 µs) that is initialized at the start of each LDE search (when a good PHR has been detected). We do not expect DW1000 users to ever see this event, however if the watchdog timer expires before the LDE has completed its RX timestamp adjustments then the LDE search will be aborted and the error will be reported by the LDEERR event status flag.
  • Page 90 Register file: 0x26 – GPIO control and status. SLP2INIT SLEEP to INIT. This event status bit is set is set to indicate that the DW1000 has completed the activities associated with awaking from SLEEP (or DEEPSLEEP) and is now in the INIT state. This reg:0F:00...
  • Page 91 CRC will be appended. If the data is written late, (i.e. the host writes to the buffer area that is part of the TX frame after the DW1000 has already consumed data from that area), then this is detected and flagged here in this TXBERR event status flag bit.
  • Page 92 The TXPUTE event status flag is READ ONLY. It will clear as soon as the DW1000 begins to send preamble, (or if the DW1000 is returned to idle). Since the TX power- up time is only a few symbol times in duration and because the TXPUTE bit clears at the start of preamble, it is unlikely that the host system will see the TXPUTE bit set.

  • Page 93: Rod Rx_Finfo

    RX_BUFFER. This field is 7-bits wide to accommodate the standard IEEE 802.15.4 UWB frames which can be up to 127 bytes long. The DW1000 also supports a non-standard mode of operation with data frame lengths up to 1023 octets, where the frame length reported is extended by the RXFLE field.

  • Page 94: Table 17: Preamble Length Reporting

    This value is updated when a good PHR is detected (when the RXPHD status bit is set). RXBR Receive Bit Rate report. This field reports the received bit rate. This information is signalled in the received frame’s PHR (see 10.4 for details). Expected values supported by the DW1000 reg:10:00 are: bits:14,13 00 = 110 kbps, 01 =850 kbps, and 10 = 6.8Mbps...
  • Page 95 These non-standard lengths cannot be signalled in the PHR; instead the DW1000 gives an estimate of the preamble length based on the RXPSR from the PHR and the RXPACC value. The estimate is reported using RXPSR and RXNSPL fields together as per Table 17above.

  • Page 96: Table 18: Rxpacc Adjustments By

    DW1000 User Manual Table 18: RXPACC Adjustments by SFD code Sequence Adjustment to RXPACC Standard 0+0-+00- -6+2-1=-5 Short (8- symbol) Standard 0+0−+00−0+0−+00–00+0−0+0+000−0−0−00+0–0−+0000++00−−−+−++0000++ -62+14-16=- Long (64- symbol) Decawave- ----+-00 -6+1-5=-10 defined 8- symbols Decawave- ----+-+--++--+00 -14+5-9=-18 defined 16- symbols Decawave- −−−−−−−+−+−−−−−−+−−+−+−−+−−+−−+−−−++−−−+++−+−+−+−−−+−−+−−−−+++00...
  • Page 97 DW1000 User Manual Register map register file 0x12 gives information about quality of reception for the current frame. This register consists of a number of sub-fields separately identified and described below: Register file: 0x12 – Rx Frame Quality Information is in the RX double-buffered swinging-set. See section 4.3 –...
  • Page 98 DW1000 User Manual Field Description of fields within Register file: 0x12 – Rx Frame Quality Information CIR_PWR Channel Impulse Response Power. This is a 16-bit value reporting the sum of the squares of the magnitudes of the accumulator from the estimated highest power portion of the channel, reg:12:04 which is related to the receive signal power.
  • Page 99 This gives the phase (7 bits = 360 degrees) of the internal carrier tracking loop at the reg:14:04 time that the RX timestamp is received. This can be used to partially compensate for the phase bits:6–0 offset in the CIR’s between two DW1000 devices. 7.2.23 Register file: 0x15 – Receive Time Stamp Length Type...
  • Page 100 DW1000 User Manual DW1000 takes a coarse timestamp of the symbol in which the RMARKER event occurs and to this adds various correction factors to give a resultant time stamp value. Please refer to section 4.1.6 – RX Message timestamp for more details of the corrections applied.
  • Page 101 Reserved – this register file is reserved Register map register file 0x16 is reserved for future use. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. 7.2.25 Register file: 0x17 – Transmit Time Stamp Length...
  • Page 102 PHR is the nominal point which is time-stamped by the IC. The IEEE 802.15.4 UWB standard calls this point the RMARKER. The DW1000 takes a timestamp of the symbol in which the RMARKER event occurs and to this adds the antenna delay to give a resultant time stamp value, of when the RMARKER is launched from the antenna.
  • Page 103 Acknowledgement Time and Response Time Register map register file 0x1A is a configuration register used for specifying turn-around times for DW1000 to use when automatically switching between TX mode and RX modes. The ACK_RESP_T register contains the following bitmapped sub-fields: REG:1A:00 –...
  • Page 104 Automatic Acknowledgementfunction. To ensure that the receiver is ready for the first preamble symbol, and assuming that the remote DW1000 has a its W4R_TIM parameter set to 0, the recommended minimum ACK_TIM settings are as follows: Recommend min.

  • Page 105: Dw1000 Calibration

    (The DW1000 has an area of OTP memory reserved for this. Please refer to section 8 –DW1000 Calibration and section 6.3 –...

  • Page 106: Figure 26: Transmit Power Control Octet

    -41.3 dBm limit while remaining in compliance with the regulations. This transmit power increase will increase the link budget and communication range. To make use of this the DW1000 includes functionality called Smart Transmit Power Control which automatically boosts the TX power for a transmission when the frame is short.
  • Page 107 When DIS_STXP is 0 and the data rate is configured to 6.8 Mbps, Smart Tx power is enabled. The DW1000 selects one of the fields of the TX Power Control register (BOOSTxxxx) depending on the overall frame duration.
  • Page 108 DW1000 User Manual Field Description of fields within Register file: 0x1E – Transmit Power Control (when DIS_STXP is 0) BOOSTP250 This value sets the power applied to the preamble and data portions of the frame during transmission at the 6.8 Mbps data rate for frames that are less than 0.25 ms duration which...
  • Page 109 DW1000 User Manual The individual sub-fields are described below. Field Description of fields within Register file: 0x1E – Transmit Power Control (when DIS_STXP is 0) TXPOWPHR This power setting is applied during the transmission of the PHY header (PHR) portion of the frame.

  • Page 110: Table 19: Reference Values Forr

    DW1000 User Manual Table 19: Reference values for Register file: 0x1E – Transmit Power Control, for Smart Transmit Power Control Example Register file: 0x1E – Example Register file: 0x1E – TX Channel Transmit Power Control values Transmit Power Control values...
  • Page 111  Sub-Register 0x2B:07 – FS_PLLCFG For correct operation of the DW1000 and compliance to the IEEE 802.15.4 UWB standard, the preamble code should be set according to the operating channel. For details of centre frequencies and preamble codes for the supported channels, please refer to section 10.5 –...
  • Page 112 DWSFD This bit enables a non-standard Decawave proprietary SFD sequence. When DWSFD is 0, and TNSSFD and RNSSFD are deasserted low, then the SFD sequence used by the DW1000 will be reg:1F:00 the one prescribed by the IEEE 802.15.4-2011 standard.
  • Page 113 Reserved – this register file is reserved Register map register file 0x20 is reserved for future use. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. 7.2.34 Register file: 0x21 – User defined SFD sequence Length...
  • Page 114 DW1000 User Manual In addition, the SFD_LENGTH part of this register file is used to select between 8 and 16 length SFD when the special Decawave defined (non-standard) SFD is being used. This is enabled by the DWSFD bit in the Register file: 0x1F –...
  • Page 115 This programming selects the 64-symbol 110 kbps defined in the IEEE 802.15.4 standard, when operating at 110 kbps. When the DW1000 is operating at 850 kbps, this programming selects a Decawave defined non- standard 8-symbol SFD, which is stronger than 850 kbps...
  • Page 116 DW1000 User Manual for details of the optimum selections of SFD sequence. Description of fields within Register file: 0x21 – User defined SFD Sub-Index Field sequence SFD_LENGTH This is the length of the SFD sequence used when the data rate is 850 kbps and higher.
  • Page 117 DW1000 User Manual Description of fields within Register file: 0x21 – User defined SFD Sub-Index Field sequence TX_LSFD_SGN0 This field sets the long (64-symbol) SFD polarity data for the transmitted SFD (Symbols 7..0) sequence. This byte covers the first 8 symbol intervals, symbols 7 to 0. The low reg:21:11 order bits define the part of the SFD sequence sent first in time.

  • Page 118: Table 21: Recommended Sfd

    DW1000 User Manual Table 21: Recommended sequence configurations for best performance TNSSFD DWSFD RNSSFD SFD_LENGTH Data reg:1F:00 Description reg:1F:00 reg:1F:00 reg:21:00 Rate bit:20 bit:17 bit:21 bits:0–7 When the DW1000 is operating at 6.8 Mbps, this programming selects the standard IEEE 6.8 Mbps...
  • Page 119 DW1000 User Manual This programming selects a Decawave defined non- standard 64- symbol which is more 110 kbps robust than standard IEEE 64-symbol improving the performance in 110 kbps mode. Table 22 below presents additional sequence programming options. Note: The selection of sequences other than the IEEE 802.15.4-2011 UWB standard compliant SFD sequence may improve...

  • Page 120: Table 22: Other Possible Sfd

    DW1000 User Manual Table 22: Other possible sequence configurations TNSSFD DWSFD RNSSFD SFD_LENGTH Data reg:1F:00 Description reg:1F:00 reg:1F:00 reg:21:00 Rate bit:20 bit:17 bit:21 bits:0–7 This programming selects the 8- symbol 850 kbps defined in the IEEE 802.15.4 standard, when operating at 850 kbps.
  • Page 121 DW1000 User Manual When the DW1000 is operating at 850 kbps, this programming selects a Decawave defined non- standard 8- symbol SFD, which is stronger than 850 kbps the standard defined still a little weaker that the data. Hence our...
  • Page 122 DW1000 User Manual When the DW1000 is operating at 6.8 Mbps or 850 kbps, this programming selects the use of a user configured with length 6.8 Mbp configurable in the range 8 to 8 to 16 16 symbols. In 850 kbps...
  • Page 123 Reserved – this register file is reserved Register map register file 0x22 is reserved for future use. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. 7.2.36 Register file: 0x23 –AGC configuration and control Length...
  • Page 124 DW1000 User Manual Register file: 0x23 –AGC configuration and control, sub-register 0x00 is a reserved register. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. Sub-Register 0x23:02 – AGC_CTRL1 7.2.36.2 Length...
  • Page 125 Reserved area 2 Register file: 0x23 –AGC configuration and control, sub-register 0x06 is a reserved area. Please take care not to write to this area as doing so may cause the DW1000 to malfunction. Sub-Register 0x23:0C – AGC_TUNE2 7.2.36.5 Length...
  • Page 126 Reserved area 3 Register file: 0x23 –AGC configuration and control, sub-register 0x10 is a reserved register. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. Sub-Register 0x23:12 – AGC_TUNE3 7.2.36.7 Length...

  • Page 127: Figure 27: Combining Edg1 And

    DW1000 User Manual REG:23:1E – AGC_STAT1 – AGC Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 128 0x24 is for control of the DW1000 synchronisation hardware. There is a separate application note giving details of the external synchronisation. Please consult with Decawave applications support team for details. The capabilities of the DW1000 with respect to external synchronisation are described briefly in section 6.1- External...
  • Page 129 DW1000 User Manual Field Description of fields within Sub-Register 0x24:00 EC_CTRL OSTRM External timebase reset mode enable. See section 6.1.1 – One Shot Timebase Reset (OSTR) Mode. reg:24:00 bit:11 7.2.37.2 Sub-Register 0x24:04 EC_RXTC Length Type Mnemonic Description (octets) 24:04 EC_RXTC External clock synchronisation counter captured on RMARKER.
  • Page 130 0x25 is a large bank of memory that holds the accumulated channel impulse response (CIR) data. To accurately determine this timestamp the DW1000 incorporates an internal (LDE) algorithm to adjust the RMARKER receive timestamp as reported in Register file: 0x15 – Receive Time Stamp.

  • Page 131: Memory

    DW1000 User Manual Description of fields within Register file: 0x25 – Accumulator CIR Sub-Index Field memory 4060 CIR[1015].real.lo8 Low 8 bits of real part of accumulator sample 1015 reg:25:FDC (1016 and last sample of CIR for the nominal 64 MHz mean PRF) 4061 CIR[1015].real.hi8...
  • Page 132 DW1000 User Manual Sub-Register 0x26:00 – GPIO_MODE 7.2.39.1 Length Type Mnemonic Description (octets) 26:00 GPIO_MODE GPIO Mode Control Register Register file: 0x26 – GPIO control and status, sub-register 0x00 is the GPIO Mode Control Register, GPIO_MODE. The GPIO_MODE register is used to select whether the GPIO is operating as a GPIO or has another special function.
  • Page 133 DW1000 User Manual Field Description of fields within Sub-Register 0x26:00 – GPIO_MODE MSGP3 Mode Selection for GPIO3/TXLED. Allowed values are: 00: The pin operates as GPIO3– This is the default (reset) state. reg:26:00 01: The pin operates as the TXLED output.
  • Page 134 DW1000 User Manual Register file: 0x26 – GPIO control and status, sub-register 0x04 is reserved. Sub-Register 0x26:08 – GPIO_DIR 7.2.39.3 Length Type Mnemonic Description (octets) 26:08 GPIO_DIR GPIO Direction control register Register file: 0x26 – GPIO control and status, sub-register 0x08 is the GPIO Direction Control Register, GPIO_DIR.
  • Page 135 DW1000 User Manual Field Description of fields within Sub-Register 0x26:08 – GPIO_DIR GDM1 Mask for setting the direction of GPIO1. (See GDM0). bit:5 GDM2 Mask for setting the direction of GPIO2. (See GDM0). bit:6 GDM3 Mask for setting the direction of GPIO3. (See GDM0).
  • Page 136 DW1000 User Manual The GPIO_DOUT register contains the following sub-fields: REG:26:0C – GPIO_DOUT – GPIO Data Output register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 137 Register file: 0x26 – GPIO control and status, sub-register 0x10 is the GPIO interrupt enable register. The GPIO_IRQE register allows a GPIO input pin to be selected as an interrupt source into the DW1000. Additional configuration registers GPIO_IMODE, GPIO_ISEN, GPIO_IBES and GPIO_IDBE allow the interrupt...
  • Page 138 DW1000 User Manual Field Description of fields within Sub-Register 0x26:10 – GPIO_IRQE GIRQE7 GPIO IRQ Enable for GPIO7 input. Value 1 = enable, 0 = disable. bit:7 GIRQE8 GPIO IRQ Enable for GPIO8 input. Value 1 = enable, 0 = disable.
  • Page 139 DW1000 User Manual Field Description of fields within Sub-Register 0x26:14 – GPIO_ISEN GISEN8 GPIO IRQ sense for GPIO8 input. Value 0 = High or Rising-Edge, 1 = Low or falling-edge. reg:26:14 bit:8 Bits marked ‘-’ are reserved and should be written as zero.
  • Page 140 DW1000 User Manual Field Description of fields within Sub-Register 0x26:18 – GPIO_IMODE GIMOD8 GPIO IRQ Mode selection for GPIO8 input. Value 0 = Level, 1 = Edge. reg:26:18 bit:8 Bits marked ‘-’ are reserved and should be written as zero.
  • Page 141 DW1000 User Manual Field Description of fields within Sub-Register 0x26:1C – GPIO_IBES GIBES8 GPIO IRQ “Both Edge” selection for GPIO8 input. Value 0 = use GPIO_IMODE, 1 = Both Edges. reg:26:1C bit:8 Bits marked ‘-’ are reserved and should be written as zero.
  • Page 142 DW1000 User Manual Field Description of fields within Sub-Register 0x26:20 – GPIO_ICLR GICLR7 GPIO IRQ latch clear for GPIO7 input. Write 1 to clear the interrupt latch. bit:7 GICLR8 GPIO IRQ latch clear for GPIO8 input. Write 1 to clear the interrupt latch.
  • Page 143 DW1000 User Manual Field Description of fields within Sub-Register 0x26:24 – GPIO_IDBE GIDBE6 GPIO6 IRQ de-bounce configuration. Value 1 = de-bounce enabled, 0 = de-bounce disabled. bit:6 GIDBE7 GPIO7 IRQ de-bounce configuration. Value 1 = de-bounce enabled, 0 = de-bounce disabled.

  • Page 144: Table 28: Register File

    27:00 Reserved Register file: 0x27 – Digital receiver configuration, sub-register 0x00 is a reserved area. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. Sub-Register 0x27:02 – DRX_TUNE0b 7.2.40.2 Length Type...

  • Page 145: Drx_Tune0B

    SFD configuration. The values needed are given in Table 30 below. Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction. Table 30: Sub-Register 0x27:02 – DRX_TUNE0b values...
  • Page 146 This programming selects the 64-symbol 110 kbps defined in the IEEE 802.15.4 standard, when operating at 110 kbps. When the DW1000 is operating at 850 kbps, this programming selects a Decawave defined non- standard 8-symbol SFD, which is stronger than 850 kbps...

  • Page 147: Drx_Tune1A

    0x04 is a 16-bit tuning register. The value here needs to change depending on the RXPRF configuration. The values needed are given in Table 31 below. Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction.

  • Page 148: Drx_Tune2

    The values needed are given in Table 33 below. Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction. Table 33: Sub-Register 0x27:08 – DRX_TUNE2values...
  • Page 149 27:22 Reserved Register file: 0x27 – Digital receiver configuration, sub-register 0x22 is a reserved area. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. Sub-Register 0x27:24 – DRX_PRETOC 7.2.40.9 Length Type...
  • Page 150 DW1000 User Manual In cases where a response is expected at a particular time, this timeout can be used to flag that the expected response is not starting on time and hence to turn off the receiver earlier than would otherwise be the case, (i.e.

  • Page 151: Table 35: Constants For Frequency Offset Calculation

    Register file: 0x27 – Digital receiver configuration, sub-register 0x28 is a read-only 21 bit register. The DW1000 receiver needs to compensate for frequency offsets between the timing references at the transmitting device and itself to successfully receive a packet. Therefore, when a packet is successfully received, the DW1000 has a sufficiently accurate estimate of the frequency offset.
  • Page 152 0x00 is a 32-bit configuration register for the transceiver. Please take care not to write other values to the reserved area of this register as doing so may cause the DW1000 to malfunction. © Decawave Ltd 2017 Version 2.12...
  • Page 153 Register file: 0x28 – Analog RF configuration block, sub-register 0x04 is a reserved register. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. Note that calibration programming steps may require writes to this register.

  • Page 154: Table 39: Register File

    Register file: 0x1F – Channel Control. The values required are given in Table 37. Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction. Table 37: Sub-Register 0x28:0B– RF_RXCTRLH values...
  • Page 155 Reserved area 2 Register file: 0x28 – Analog RF configuration block, sub-register 0x10 is a reserved register. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. Sub-Register 0x28:2C – RF_STATUS 7.2.41.6...
  • Page 156 DW1000 User Manual Field Description of fields within Sub-Register 0x28:2C – RF_STATUS CPLLLOCK Clock PLL Lock status. This is a READ ONLY status flag. CPLLLOCK indicates that the digital clock PLL is locked. Note: The PLLLDT bit in Register file 0x24:00 –EC_CTRL...
  • Page 157 Reserved – this register file is reserved Register file: 0x29 – Reserved is reserved. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. 7.2.43 Register file: 0x2A – Transmitter Calibration block Length...
  • Page 158 2.5 µs to allow the SAR time to complete its reading. reg:2A:00 bit:0 Bits marked ‘-’ in register 0x2A:00 are reserved and should always be written as zero to avoid any malfunction of the DW1000. reg:2A:00 bits:15–1 Sub-Register 0x2A:03 – TC_SARL 7.2.43.2...
  • Page 159 SAR A/D sampling of the battery voltage monitor output reg:2A:06 during wakeup. For this to be valid the DW1000 has to have been reset or woken from bits:7–0 sleeping with the ONW_RADC bit enabled in the (saved) Sub-Register 0x2C:00 –...
  • Page 160 DW1000 User Manual Sub-Register 0x2A:08 – TC_PG_CTRL 7.2.43.4 Length Type Mnemonic Description (octets) 2A:08 TC_PG_CTRL Transmitter Calibration – Pulse Generator Control Register file: 0x2A – Transmitter Calibration block, sub-register 0x08, is a 16-bit control register that contains the following bitmapped sub-fields: REG:2A:08 –...
  • Page 161 The TC_PGDELAY value will not give the same bandwidth for varying temperatures. The PG_COUNT value, however, will give a stable bandwidth across all temperatures. It is taken as a reference as the DW1000 has a pulse generator auto-calibration procedure; the procedure takes a PG_COUNT value and calculates the TC_PGDELAY value from this.
  • Page 162 DW1000 User Manual Sub-Register 0x2A:0C – TC_PGTEST 7.2.43.7 Length Type Mnemonic Description (octets) 2A:0C TC_PGTEST Transmitter Calibration –Pulse Generator Test Register file: 0x2A – Transmitter Calibration block, sub-register 0x0C is an 8-bit configuration register for use in setting the transmitter into continuous wave (CW) mode. This CW mode is employed during the crystal trimming operation which may be done at module manufacturing stage as part of calibrating the crystal oscillator’s operating frequency.
  • Page 163 Register file: 0x1F – Channel Control). The values required are given in Table 43. Please take care not to write other values to this register as doing so may cause the DW1000 to malfunction. Table 43: Sub-Register 0x2B:07 – FS_PLLCFG values...
  • Page 164 For details of the use of this register please refer to section 8.1 – IC Calibration – Crystal Oscillator Trim. N.B.: Bits 7:5 must always be set to binary “011”. Failure to maintain this value will result in DW1000 malfunction. REG:2B:0E – FS_XTALT – Crystal Trim Setting...
  • Page 165 The AON block contains a low-power configuration array that remains powered-up as long as power (from the battery, for example) is supplied to the DW1000 via the VDDAON pin. User configurations, from SPI accessible host interface registers, can be automatically saved in the AON memorywhen the DW1000 enters SLEEP or DEEPSLEEP states and automatically restored from the AON memorywhen the DW1000 wakes from sleeping.
  • Page 166 Register file: 0x2C – Always-on system control, sub-register 0x00 is a 16-bit configuration register that is used to control what the DW1000 IC does as it wakes up from low-power SLEEP or DEEPSLEEP states. The AON_WCFG register contains the following bitmapped sub-fields: REG:2C:00 –...
  • Page 167 ONW_LLDE On Wake-up load the LDE microcode. The LDE algorithm is implemented in a microcode that is stored in a special ROM area on the DW1000 but run from a RAM area. Before the reg:2C:00 LDE is run the DW1000 has to copy it from ROM to RAM. The LDE algorithm is responsible...
  • Page 168 Description of fields within Sub-Register 0x2C:02 – AON_CTRL RESTORE When this bit is set the DW1000 will copy the user configurations from the AON memory to the host interface register set. The RESTORE bit will auto clear when this command is reg:2C:02 executed.

  • Page 169: Table 46: Configurations Maintained In The

    DW1000 User Manual Table 46: Configurations maintained in the AON Memory Array Configuration Register Configuration Register Register file: 0x03 – PAN Identifier and Short Address Sub-Register 0x28:0B– RF_RXCTRLH Register file: 0x04 – System Configuration Sub-Register 0x28:0C– RF_TXCTRL Register file: 0x08 – Transmit Frame Control Sub-Register 2A:0B –...

  • Page 170: Figure 28: Flow Chart For Direct Read Of

    DW1000 User Manual Sub-Register 0x2C:03 – AON_RDAT 7.2.45.3 Length Type Mnemonic Description (octets) 2C:03 AON_RDAT AON Direct Access Read Data Result Register file: 0x2C – Always-on system control, sub-register 0x03 is an 8-bit register used to return the result of a direct access read of a location in the AON memory array. The location to read from is specified by Sub- Register 0x2C:04 –...
  • Page 171 Description of fields within Sub-Register 0x2C:06 – AON_CFG0 SLEEP_EN This is the sleep enable configuration bit. In order to put the DW1000 into the SLEEP state this bit needs to be set and then the configuration needs to be uploaded to the AON using the...
  • Page 172 AON_CFG1. If none of these wakeup mechanisms are enabled and the DW1000 is put into DEEPSLEEP mode then there will be no way to take the IC out of sleep except by removing power at the VDDAON pin, (and short it to 0 volts to hasten the power down of the IC).
  • Page 173 (e) Set UPL_CFG to 1, to apply the new sleep time and enable the counter in the AON. SMXX This bit needs to be set to 0 for correct operation in the SLEEP state within the DW1000. By reg:2C:0A default this bit is set to 1. The host system should set this bit to zero as part of initialisation or...

  • Page 174: Table 47: Register File

    NOTE: Programming OTP memory is a one-time only activity, any values programmed in error cannot be corrected. Also, please take care when programming OTP memory to only write to the designated areas – programming elsewhere may permanently damage the DW1000’s ability to function normally. For more details of the OTP memory please refer to section 6.3 –...
  • Page 175 DW1000 User Manual OFFSET in Register 0x2D Mnemonic Description 0x0E OTP_SRDAT OTP SR Read Data 0x12 OTP_SF OTP Special Function Sub-Register 0x2D:00 – OTP_WDAT 7.2.46.1 Length Type Mnemonic Description (octets) 2D:00 OTP_WDAT OTP Write Data Register file: 0x2D – OTP Memory Interface, sub-register 0x00 is a 32-bit register.
  • Page 176 DW1000 User Manual Register file: 0x2D – OTP Memory Interface, sub-register 0x06 is a 16-bit register used to control the operation of the OTP memory through the process of reading and writing. The OTP_CTRL register contains the following fields: REG:2D:06 – OTP_CTRL – OTP Control...
  • Page 177 LDE functionality. The LDE algorithm is implemented in a microcode that is stored in a special ROM area on the DW1000 but run from a RAM area. After powering up the DW1000 (or after exiting SLEEP or DEEPSLEEP states) the LDE RAM is empty. Before the LDE is run the code has to be copied from ROM to RAM.
  • Page 178 DW1000 User Manual Field Description of fields within Sub-Register 0x2D:08 – OTP_STAT Reserved. Bits marked ‘-’ are reserved. reg:2D:00 bits:various Sub-Register 0x2D:0A – OTP_RDAT 7.2.46.5 Length Type Mnemonic Description (octets) 2D:0A OTP_RDAT OTP Read Data Register file: 0x2D – OTP Memory Interface, sub-register 0x0A is a 32-bit register.

  • Page 179: Table 48: Receiver Operating Parameter Sets

    7.2.46.8 Receiver operating parameter sets The DW1000 receiver has the capability of operating with specific parameter sets that relate to how it acquires the preamble signal and decodes the data. Three distinct operating parameter sets are defined within the IC for selection by the host system designer depending on system characteristics. Table 48 below lists and defines these operating parameter sets indicating their recommended usages.
  • Page 180 DW1000 User Manual Description performance optimization again comes at a cost, which is that the total crystal offset between transmitter and receiver must be kept very tight, at or below about 1 ppm. This might be done, for example, by using very high quality 0.5 ppm TCXOs in both the transmitter and the receiver.
  • Page 181 DW1000 User Manual Register file: 0x2E – Leading Edge Detection Interface, sub-register 0x0000 is a 16-bit status register reporting the threshold that was used to find the first path. This threshold is calculated based on an estimate of the noise made during the LDE algorithm’s analysis of the accumulator data. This threshold report may be of diagnostic interest in certain circumstances.
  • Page 182 DW1000 User Manual Sub-Register 0x2E:1002 – LDE_PPAMPL 7.2.47.4 Length Type Mnemonic Description (octets) 2E:1002 LDE_PPAMPL LDE Peak Path Amplitude Register file: 0x2E – Leading Edge Detection Interface, sub-register 0x1002, is the LDE Peak Path Amplitude (LDE_PPAMPL) register. This is a 16-bit status register reporting the magnitude of the peak signal seen in the accumulator data memory during the LDE algorithm’s analysis, (the index at which this occurs is reported in...
  • Page 183 DW1000 User Manual Table 50: Sub-Register 0x2E:1806– LDE_CFG2 values Value to program to RXPRF configuration Sub-Register 0x2E:1806– LDE_CFG2 (1) = 16 MHz PRF 0x1607 (2) = 64 MHz PRF 0x0607 Sub-Register 0x2E:2804 – LDE_REPC 7.2.47.7 Length Type Mnemonic Description (octets)

  • Page 184: Table 49: Register File

    DW1000 User Manual RX_PCODE LDE_REPC RX_PCODE LDE_REPC configuration value to set configuration value to set 0x3AE0 0x28F4 0x3850 0x3332 0x30A2 0x3AE0 0x3850 0x3D70 NB: When operating at 110 kbps the unsigned values in Table 51 have to be divided by 8, (right shifted 3, shifting zeroes into the high order bits), before programming into Sub-Register 0x2E:2804 –...
  • Page 185 DW1000 User Manual (octets) 2F:00 EVC_CTRL Event Counter Control Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x00 is the event counter control register. REG:2F:00 – EVC_CTRL – Event Counter Control 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - 0 0 Fields in the EVC_CTRL register are intended to be self-clearing.
  • Page 186 DW1000 User Manual REG:2F:04 – EVC_PHE – PHR Error Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 187 DW1000 User Manual REG:2F:08 – EVC_FCG – Frame Check Sequence Good Event Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 188 DW1000 User Manual REG:2F:0C – EVC_FFR – Frame Filter Rejection Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 189 DW1000 User Manual REG:2F:10 – EVC_STO – SFD Timeout Error Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 190 DW1000 User Manual REG:2F:14 – EVC_FWTO – RX Frame Wait Timeout Event Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 191 DW1000 User Manual REG:2F:18 – EVC_HPW – Half Period Warning Counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...
  • Page 192 Register file: 0x2F – Digital Diagnostics Interface, sub-register 0x1C is a reserved register. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. Sub-Register 0x2F:24 – Digital Diagnostics Test Mode Control 7.2.48.15...
  • Page 193 Control, sub-register 0x00 is a 32-bit control register relating to enabling clocking to various digital blocks within the DW1000. This register also has a field allowing a software applied reset to be applied to the IC. The PMSC_CTRL0 register contains the following sub-fields: ©...
  • Page 194 01: Force system clock to be the 19.2 MHz XTI clock. 10: Force system clock to the 125 MHz PLL clock. (If this clock is not present the DW1000 will essentially lock up with further SPI communications impossible. In this case an external reset will be needed to recover).
  • Page 195 The de-bounce filter circuit reg:36:00 clocks the GPIO inputs into the DW1000 and removes short transients by requiring that the bit:18 input persists for two cycles of this clock before it will be seen by the interrupt handling logic.
  • Page 196 ARX2INIT Automatic transition from receive mode into the INIT state. If the ARX2INIT bit is set then the DW1000 will automatically transition into the INIT state after a receive attempt so long as reg:36:04 there are no unmasked interrupts pending. This control is used to enableLow duty-cycle SNIFF bit:1 mode.
  • Page 197 Kilohertz clock divisor. This field specifies a clock divider designed to give a kilohertz range reg:36:04 clock that is used in the DW1000 for the LED blink functionality and also for the GPIO de- bits:31–26 bounce functionality. The input to the kHz divider is the 19.2 MHz XTI clock (which is the raw 38.4 MHz XTAL ÷...

  • Page 198: Table 53: Register File

    PMSC reserved area 1 Register file: 0x36 – Power Management and System Control, sub-register 0x08 is a reserved register. Please take care not to write to this register as doing so may cause the DW1000 to malfunction. Sub-Register 0x36:0C – PMSC_SNOZT 7.2.50.4...
  • Page 199 0x0B74 should be written back to this register. bits:15–0 Note that TX fine grain power sequencing must be disabled if an external power amplifier is being used with the DW1000. Sub-Register 0x36:28 – PMSC_LEDC 7.2.50.7...
  • Page 200 0x3F Register map register files 0x36 through 0x3F are reserved for future use. Please take care not to write to these registers as doing so may cause the DW1000 to malfunction. © Decawave Ltd 2017 Version 2.12 Page 200 of 242...

  • Page 201: Ic Calibration - Crystal

    An area of the DW1000’s OTP memory has been set for module test calibration parameters. The host system software will use this calibration data during DW1000 configuration to optimise the DW1000 performance.
  • Page 202 The DW1000 is configured to transmit a continuous wave (CW) signal at a particular channel frequency. It is suggested that channel 5 is used because the higher the frequency the easier it is to observe step changes in the output.

  • Page 203: Ic Calibration - T

    IC Calibration – Transmit power and spectrum In order to maximise range, DW1000 transmit power spectral density (PSD) should be set to the maximum allowable for the geographic region of deployment. For most regions this is -41.3 dBm / MHz. DW1000 is © Decawave Ltd 2017 Version 2.12...

  • Page 204: Table 54: Register Accesses Required For Transmitter

    As this is an analog circuit, there will be some variation in output power levels from IC to IC and hence DW1000 should be calibrated and the calibrated power setting stored in the OTP memory. DW1000 provides the facility to adjust the transmit power in coarse and fine steps; 3 dB and 0.5 dB nominally. It also provides the ability to adjust the spectral bandwidth.
  • Page 205 DW1000 User Manual 1. Write the correct value for the selected channel to Sub-Register 0x28:0C– RF_TXCTRL, e.g. 0x045CA0 for channel 2. 2. Write an appropriate value for TX_POWER to Register file: 0x1E – Transmit Power Control, e.g. for channel 2 at 16 MHz PRF, write 0x75757575. See Table 20.

  • Page 206: Ic Calibration - Antenna

    In order to measure range accurately, precise calculation of timestamps is required. To do this, a delay called the antenna delay must be known. The DW1000 allows this delay to be calibrated and provides the facility to compensate for delays introduced by PCB, external components, antenna and internal DW1000 delays.

  • Page 207: Figure 30: Transmit And Receivea

    DW1000 User Manual To calibrate the antenna delay, range is measured at a known distance using 2 DW1000 systems. Antenna delay is adjusted until the known distance and reported range agree. The antenna delay can be stored in OTP memory.
  • Page 208 The DW1000 ranging algorithm will calculate the time of reception of a packet in order to estimate the range to the transmitter. The receiver antenna delay is a constant value representing the propagation time of the received signal from the antenna to the receiver point of timestamp calculation.

  • Page 209: Operational Design Choices When Employing The Dw1000

    Operating range The operational range of the DW1000 depends on the frame data rate and the preamble length. In free- space, line-of-sight (LOS), this may vary from 60 m at the 6.8 Mbps data rate to up to 250 m at the 110 kbps data rate.

  • Page 210: Power Consumption

    As described above, frames with lower data rate have the largest operating range. Such messages by their nature also take longer to send and, as this means that the DW1000’s transmitter needs to be on for a longer period, the result is that more power is consumed than for faster messages. The quantity of data being transferred also has a bearing on this, i.e.

  • Page 211: Low-Duty Cycle - Air Time

    DW1000 User Manual This 18% air utilisation comes into play when deploying a population of RTLS tags periodically blinking. Table 58 gives some indications of the blink transmission rates corresponding to some typical data rate / preamble length combinations and with a minimum 12-byte blink frame sending the Tag ID. The number of transmissions that can be made within the 18% air-utilisation is highest for the shortest duration frame (64- symbol preamble and 6.8 Mbps data rate) and lowest at the long range 110 kbps data rate with its long...

  • Page 212: Location Schemes

    DW1000 User Manual Location schemes This part of the discussion on operational design choices relates to RTLS location schemes. Some of the ideas and points discussed may be more generally applicable. In general to locate a mobile node measurements are needed to be referenced to a number of fixed known location “anchor”...

  • Page 213: General Considerations

    DW1000 User Manual In an RTLS the accuracy of the DW1000’s RX timestamps can give sub 10 cm resolution. Note, however that the geometry of anchors with respect to the tag can smear the accuracy of the calculated location when individual measurements are combined.
  • Page 214 DW1000 User Manual Name Description Slotted listening In this technique all devices listen for a periodic beacon from which slots are timed and then listen in their assigned slot for a message. The amount of slots and the amount of listening is dependent on the network size and required response times.

  • Page 215: Appendix 1: The Ieee 802.15.4 Uwb Physical Layer

    This appendix gives an introduction to the modulation scheme and frame structure of the UWB physical layer as specified in the IEEE 802.15.4 – 2011 standard and as implemented by the DW1000 transceiver IC. This is useful in understanding the operation of the DW1000 transceiver and its configuration options.

  • Page 216: 10.3 Synchronisation Header Modulation Scheme

    110 kbps data rate the PHR is transmitted as per the 110 kbps data coding, again without the Reed Solomon code, giving them a bit rate is just over 120 kbps. The DW1000 supports 110 kbps, 850 kbps, and 6.8 Mbps data rates but does not support the 27 Mbps data rate.

  • Page 217: 10.4 Phy Header

    64 nominal 1017.63 The standard defines PSR settings of 16, 64, 1024 and 4096. The DW1000 supports these (although it will not receive frames with preamble length below 64 symbols) and in addition supports PSR settings of 128, 256, 512, 1536 and 2048.

  • Page 218: 10.5 Uwb Channels And Preamble Codes

    Figure 33: PHR bit assignment Figure 33 above shows the bits of the PHR. These are transmitted bit-0 first in time. The DW1000 fills in the Data Rate, Frame Length, Ranging Packet, and Preamble Duration fields of the PHR based on the user configuration of the appropriate parameters in Register file: 0x08 –...

  • Page 219: 10.6 Additional Details On The Standard

    The idea is to make it more difficult to eavesdrop or spoof, by randomly changing the DPS preamble codes in a mutually agreed sequence only known to the valid participants. This is supported by the DW1000 where at 64 MHz PRF the preamble codes additionally available for DPS are: 13, 14, 15, 16, 21, 22, 23 and 24.

  • Page 220: Appendix 2: The Ieee 802.15.4 Mac Layer

    Figure 34: General MAC message format The MAC header is parsed by the DW1000 as part of the frame filtering function to determine if its destination address matches the IC’s address information programmed in Register file: 0x01 – Extended Unique Identifier Register file: 0x03 –...

  • Page 221: Mac Header

    This bit when set indicates the presence of the Auxiliary Security Header field within the MAC header and indicates that the MAC may be employing security processing of the frame payload for authentication and/or encryption. The DW1000 does not incorporate any facilities for security, so if the frame is © Decawave Ltd 2017 Version 2.12...
  • Page 222 This bit indicates that the sending device has more data for the recipient. The reader is referred to the standard [1] for the details of this MAC protocol. The DW1000 receiver does not use the frame pending field in the receiver so it is up to the host software to handle it appropriately. The host software is also responsible for forming the TX frame and setting the frame pending bit appropriately.

  • Page 223: Table 63: Destination Addressing Mode Field Values

    [1], which says the frame version field shall be set to 0x00 to indicate a frame compatible with IEEE 802.15.4-2003 and 0x01 to indicate an IEEE 802.15.4 frame. The DW1000 understands this frame version field rules and will reject receive frames that do not have the correct frame version. Please refer to section 5.2 –...
  • Page 224 Control, inserting the 2-octet FCS as the last two octets of the data payload. The DW1000 will not do any other MAC level transmit processing. So, it is up to the host system software to prepare the correctly formatted frame conforming to the IEEE 802.15.4 standard MAC if this is required.

  • Page 225: Figure 36: Single - Sided Two

    The chosen two-way ranging algorithm is implemented by host system software and is not a feature of the DW1000. The DW1000 just provides the facilities for message time-stamping and precise control of message transmission times that enable these algorithms. See section 4.1.6 –...

  • Page 226: Table 65: Typical Clock Induced Errors In Ss-Twr Time Of

    DW1000 User Manual In this scheme the error in the measured is given by the following: - prop Table 65: Typical clock induced errors in SS-TWR time of flight estimation clock error 2 ppm 5 ppm 10 ppm 20 ppm...

  • Page 227: Figure 37: Double - Sided Two

    DW1000 User Manual 12.3 Double-sided Two-way Ranging 12.3.1 Using 4 messages Double-sided two-way ranging (DS-TWR), is an extension of the basic single-sided two-way ranging in which two round trip time measurements are used and combined to give a time-of-flight result which has a reduced error even for quite long response delays.
  • Page 228 It can be difficult to achieve a situation where the reply times at each device are the same although the use of the DW1000 delayed send feature simplifies this; the calculations required at each device may not be the same. For example, the final message from device A to device B will often need to embed the send and receive times into the packet so that device B can calculate the time of flight.
  • Page 229 DW1000 User Manual As the difference in reply time of the two devices increases there is a linear increase in the error in the calculated time of flight which can approach 30 cm for a reply-time difference of 100 µs.

  • Page 230: Figure 39: Ranging To 3 Anchors With Just

    DW1000 User Manual round1C reply2C round1B reply2B round1A reply2A time Poll RespA RespB RespC Final The Final message communicates the tag’s RMARKER and T times to the anchors, which round reply propA propA propA each calculate the range to the tag as follows.
  • Page 231 DW1000 User Manual © Decawave Ltd 2017 Version 2.12 Page 231 of 242...
  • Page 232 DW1000 User Manual 12.3.4.4 Infrastructure-less Peer-to-peer networks In the case of a peer-to-peer network of N mobile nodes where each node wants to find its distance to every other peer node as part of solving their relative location then this is ½N(N-1) distance measurements. For example, for a 5 node system, this is 10 distance measurements.
  • Page 233 A scheme that automatically adjusts the gain of the DW1000 receiver automatic gain control depending on the power in the received signal A frame sent by the DW1000 in response to a received frame indicating acknowledgement successful reception. DW1000 allows the automatic generation of such (frame) frames when appropriately configured.
  • Page 234 NLOS non line of sight sight between the transmitter and the receiver one-time Internal memory in DW1000 that can be programmed once to store programmable various identification and calibration values (memory) A group of preamble symbols which are correlated together in the preamble detection process in the receiver.
  • Page 235 TDOA arrival TDOA measurements at different locations can be used to uniquely determine the position of the transmitter. Refer to Decawave’s website for further information. The time taken for a radio signal to travel between the transmitting time of flight...

  • Page 236: Table 67: Document History

    – Part 15.4: Low-Rate Wireless Personal Area Networks (LR-WPANs). IEEE Computer Society Sponsored by the LAN/MAN Standards Committee. Available from http://standards.ieee.org/. [2] APH010 DW1000 Inter-Channel Interference: How transmissions on one DW1000 channel can affect other channels and how to minimize that effect. Available on www.decawave.com...
  • Page 237 Inclusion of note re half duplex operation only Modification of section heading 2.5.5.4 to refer to NTM rather than NSTD Update to VDDIO for OTP programming to be consistent with DW1000 data sheet Modification to CPLOCK bit description Modification to description of CLKPLL_LL bit Modification to Table 26 –...

  • Page 238: Trim

    RXPACC field of RX_FINFO updated to describe adjustments that can be made to the count to calculate more accurate receive signal power as used in calculations in section 4.7. RX_BUFFER register type changed to read-only. DWSFD field of CHAN_CTRL register description updated to specify Decawave-defined SFD sequences RXPACC_NOSAT added to address 0x27, subaddress 0x2C Subregister 0x27:2C, RXPACC_NOSAT added EVC_CTRL register description corrected to describe write-to-enable behaviour.
  • Page 239 DW1000 User Manual Page Change Description Update of version number to v2.08 Various typographical changes and formatting corrections Corrections to OTP memory map to be consistent with APS012 Description of FINFO reg updated to indicate that RNG bit is bit 15 and not bit 10...
  • Page 240 DW1000 User Manual Revision v2.10 Page Change Description Update of version number to v2.10 Various typographical changes and formatting corrections Correct the fixed value in the first three hex digits to be 0x100 and not 0x101 as previously suggested. 96 / 100...
  • Page 241 DW1000 User Manual Revision v2.12 Page Change Description Update of version number to v2.12 To read OTP OTP_RDAT change 2A.04 to 2D:0A (see also 7.2.46.5) Row 5 removed. New note on requirement for isolation of VDDPA1 and VDDPA2 if using Tx gain setting 000 Note added to point out that GPIO clocks have to be on to use GPIO lines.
  • Page 242 (RTLS) and Ultra Low Power Wireless Transceivers in areas as diverse as manufacturing, healthcare, lighting, security, transport, and inventory and supply-chain management. For further information on this or any other Decawave product contact a sales representative as follows: - Decawave Ltd,...

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