Gemplus GPR400 Reference Manual page 12

Smartcard reader / writer
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other bits:
Smartcard Register 1
Read only access: Address FBAh in the Attribute Memory.
bit 4:
bit 7:
other bits :
Smartcard Register 2
Read only access: internal use : Address FBCh in the Attribute Memory
Clock and Control Register
Read only access: internal use : Address FBEh in the Attribute Memory
Handshake Register
Handshake register (read and write): address 00h in the I/O buffer.
bit 0 :
bit 1 :
bit 2 :
bits 3 to 7 : for PRG control (see Using PRG section)
© GEMPLUS
Internal use.
= 1:
Smartcard was pulled-out
= 0:
Smartcard is in the reader
= 1:
Smartcard inserted
= 0:
no Smartcard inserted
internal use
Master Reset : A "RESET GPR" sets this bit to a minimum
time of 5 microseconds and waits for 20 milliseconds. This
command is the first action to perform after a "POWER
DOWN GPR": it reactivates the embedded microprocessor.
Note that the GPR400 is automatically reactivated when
inserted into the PCMCIA socket.
INTR : GPR400 interrupt request: After sending the GPR400
command in the I/O buffer, the host must set this bit to 1 in
order to launch the execution phase. This bit will be reset by
the GPR400 after the execution of the command.
BUSY/IREQ : this bit is an image of the PCMCIA pin IREQ
(Interrupt Request). The GPR400 sets this bit to 1 after
command execution, forcing the IREQ pin to 0. The host can
receive the command response and then reset this bit to 0.
SENDING COMMANDS TO THE READER
7

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