Integra-T A/D And Digipot; Wake-Up Circuit; Power Supply - Dataradio Integra-TR Technical Manual

synchronous bit stream is then fed to CPU, SIO-
A for further processing and convertion to
asynchronous format before delivery to the RS-
232 driver and to the user port.
4.3.5 Integra-R A/D and DIGIPOT
An 8 channel, 8-bit successive approximation
A/D converter, type ADC0838 (U4), is inter-
faced to CPU (U17) and Peripheral (U21).
CH0 and CH1 are connected to the positive and
negative peak detector of the modem section.
The software can thus read the positive or nega-
tive value of an RX signal, or using the differ-
ential mode, the actual peak-to-peak RX signal
value.
CH3 is used to measure the radio RSSI signal
which was amplified by U7A.
CH4 is connected to the radio diagnostic signal
(P3-14). This pin is used to output an analog
signal corresponding to the power output and
the reflected signal.
CH5 is connected to U6 (LM50), a temperature
sensor with a -40 to +125°C range.
CH6 is used to read the SWB+ voltage after
proper scaling into the 0-5 V range.
CH7 and CH8 are connected to EXT SIGNAL 1
and 2. A 2:1 divider and protection circuit is
inserted between both external signals and the
A/D.
The EXTERNAL SIGNAL 1 and 2 pins are also
connected to U21 at PB6 and PB7 through tran-
sistors Q3 and Q4, and thus can be used for
ANALOG INPUT or DIGITAL OUTPUT
(available on some Integra versions).
EXT_SIGNAL2 is also connected to the rx test
point RX-TP through U8A (74HC4066). Under
software control the RX-TP (scaled down by 2)
is thus available on the power connector for
trouble-shooting purposes.
A 4 channel digital potentiometer type (U5) is
used to adjust the RX SIGNAL, TX
MODULATION, CARRIER FREQUENCY and
CARRIER DETECT THRESHOLD.
120 40101-103
An 8 channel, 8-bit successive approximation
A/D converter, type AD0838 (U9), is interfaced
to CPU (U18) and Peripheral (U20).
U19 generates a power-on reset for the CPU and
U6 is a temperature sensor used by the firmware
to compensate for variations in RSSI.
The RSSI signal from the transceiver is ampli-
fied and filtered by U7A, it is then compared to
a threshold value set by a digital potentiometer
(U5A). The output of the comparator (U7B) is
used to change the hold time of both peak de-
tectors at the beginning of the receive packet.
4.3.6

Wake-Up Circuit

The wake-up circuit for Integra-R consists of a
50 ms monostable circuit that is triggered by the
rising edge of a SLEEP signal from the CPU
(U17). The falling edge of this 50 ms pulse (end
of pulse) is connected to the \NMI of the CPU
and thus will wake up the CPU from SLEEP
mode after 50 ms.
When exiting SLEEP mode on a \NMI, the CPU
firmware will increment a counter, then return
to SLEEP until it reaches a limit set by a soft-
ware parameter. When the programmed count is
reached the CPU will wake up the radio and the
RS232 driver, program the synthesizer, and
watch for channel activity.
While in sleep mode (during the 50 ms pulse) an
active RTS from either communication port will
reset (terminate) the 50 ms pulse so that its fal-
ling edge will restart the CPU immediately.
The CPU will check to see if either RTS signal
is valid each time it is restarted by the \NMI.
The firmware will only start the sleep timer after
checking that all "wakeup" inputs are inactive.
4.3.7

Power Supply

The 13.3 volt DC power input is protected by a
3 amp fuse and reverse protected by a diode.
A 5 volt, low voltage regulator (U12) is used to
power all digital functions and another 5 volt,
low voltage regulator is used to control the
analog +5V_SW voltage in the sleep mode.
18 Integra T Technical Manual