Chapter 2 - Operational Amplifiers; Introduction; Dual Dc Amplifier Patching - EAI 580 Reference Handbook

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CHAPTER 2
OPERATIONAL AMPLIFIERS
2.1.
INTRODUCTION
The operational amplifier is the basic computing element in an analog computer.
The amplifier may be used in conjunction with appropriate networks to perform
linear computations such as summation, integration, multiplication by a con-
stant, and inversion.
Accessory components permit use of the amplifier for
nonlinear operations such as multiplication and division of variables, and the
generation or analytic or arbitrary functions.
There are two amplifiers used in the 580.
These are:Dual DC Amplifier, Model
0.6.614-1 and Quad DC Amplifier, Model 6.704-2.
Figure 2.1 shows the patch
block layout and simplified schematic of each amplifier type and the associated
resistor network.
2.2
DUAL DC AMPLIFIER PATCHING
The input and output terminations of the dual amplifier and dual resistor net-
works are terminated at the pre-patch panel and are arranged for ease of patching.
The nonlinear components are also located in close proximity to the amplifiers
for ease of patching and short patch cord runs.
Patching an amplifier for use with an integrator network, or one of the non-
linear components, is covered in the separate sections of this manual pertain-
ing to the particular component.
This section is limited to the description of
the amplifier used in conjunction with a resistor network.
Figure 2.2 illustrates two of the more ·common patching arrangements for the
Model 0.6.614-1 Amplifier.
The patching shown for the upper amplifier (Figure
2.2a) makes use of the standard 4-pin bottle plug and provides the summing
circuit shown schematically in Figure 2.2b.
This configuration has two gain-
of-one and two gain-of-ten inputs.
The basic programming symbol for this cir-
cuit is shown in Figure 2.2c.
Note that the amplifier address number is norm-
ally placed in the triangle.
Normally, only those inputs to be used are shown.
The lower amplifier (Figure 2.2a) is patched for one gain-of-one and three gain-
of-one-tenth inputs using two 2-pin bottle plugs.
The simplified schematic and
programming symbol for this configuration are illustrated in Figures 2.2d and
e.
Additional input resistors can be made available by connecting the
RJ
terminations of different resistor networks together as shown in Figure 2.2f.
Resistors may be patched in series or parallel in the input or feedback circuit
to obtain desired gains.
Some of these configurations are summarized in
Appendix 1.
2-1

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