Video; Ram Addressing; Alphanumeric Format - Radio Shack TRS-80 Technical Manual

binary
11,
Z66
will
output
a
very
narrow
pulse
which
clears
Z32
back to zero.
The 60 Hz
at
pin
1 1
is
used by the sync
generator
circuits
to
produce
the vertical
sync
for the
monitor.
VIDEO
RAM ADDRESSING
During our discussion of the system block diagram,
you
noticed that the video
RAMs
must
be addressed
from two
sections.
The
CPU
must
address video
RAMs
to read or
write data
from
or to specific locations.
The
divider
chain
must
also
address video
RAM
so that data
contained
in
memory
can be processed and displayed
on
the screen.
The
video
RAMs
are
addressed
either
by
the
CPU
or
by the
divider chain
through the use of three multiplexers.
Z64,
Z49
and Z31
are
the three multiplexers used
for
video
RAM
addressing.
From
the divider chain, there
are
10
address
lines
that
will
be used to address video
RAM.
The
chain conditioning
logic
supplies
one
address
—
C1.
Z65
supplies three addresses
-
R1,
C2
and C4.
Z50
supplies
three addresses
-
C8,
C16
and C32.
Z32
supplies the
rest
-
R2,
R4 and
R8. Imagine an array of rectangles;
16
rec-
tangles vertically
and 64
rectangles horizontally.
You
would
have
a total
of
1024
rectangles.
You
could specify
any one
rectangle
by
saying, "Starting
at
the
top
left
hand
corner,
go
down
four
rows and
go
to the
right
18 columns."
The
16
rows could be assigned
a
binary
number
from
to 15.
The
64
columns could be assigned
a
binary
number
from
to 63.
Rectangle
0—0
would
be
in
the
upper
left
hand
corner of the
array.
Rectangle
15—63
would
be
in
the lower
right
hand
corner.
Four
bits
of binary
information
would
therefore specify
any one of the 16 rows.
It
takes
six bits
of binary data to specify
any one of the
64
columns. This
is
exactly the addressing
format used by
the
counter
chain.
C1, C2, C4, C8,
C16
and
C32
specify
any column. R1, R2,
R4
and
R8
specify
a
row.
The row/column
addressing
for-
mat
is
very
useful
in
troubleshooting video
problems
in
the
TRS-80.
The column and row
address
outputs
from
the divider chain
are
applied to the "1 " inputs of the multiplexer. Part of the
CPU's address bus
is
tied
to the
"0"
input of the
multi-
plexer.
The
outputs of the multiplexer
are tied
to the video
RAMs
or logic
around them. We've
got inputs
and outputs;
how
about
control?
Do
you remember
the
signal
VID*
that
we
generated
back
in
the address
decoding
discussion?
We
said
VID*
will select
the video
RAMs.
Notice that pin
1
of
the
3
multiplexers
is
tied to
VID*.
When
the
CPU
wants
control over the video
RAM,
the address
decoder
recognizes
the video
RAM
address
and causes
VID*
to
go low.
When
VID*
is
low, the multiplexer switches the
"0"
inputs over
to the multiplexer outputs.
The
counter chain addresses
are
switched out of
the circuit,
and
the
CPU
has control
over
video
RAM. When VID*
goes
back
high,
the
CPU
is
switch-
ed out and
the
counter chain takes over.
Most
of the time,
the counter chain
is
in
control of video
RAM.
The
CPU
only takes charge
when
it
needs
to.
You
can see
on
the
display screen
when
the
CPU
robs the counter chain of
video
RAM
control.
Ever notice black streaks
all
over the
screen while graphics
are
being
drawn? These
streaks are
the
result
of the
counter chain
losing
control over video
RAM.
Aside from chain
and
CPU
address, there are inputs to the
multiplexer
we
have not yet
mentioned.
The
first
of these
inputs
is
the resistor at pins
13 and 6 of
Z49. These
two
inputs,
which
are
not needed
in
the
counter
chain's
control
over video
RAM,
are pulled
up
to 5
volts
by R49.
Output
pins
12 and 7
correspond
to the inputs at pins
13
and
6.
When
the chain has control over video
RAM,
pinsJI2
and 7
output
a
steady state high. Pin 12
goes to the
R/W
(Read/
Write) control of
all
the
RAMs.
Since the
counter chain
never
stores
data
in
RAM
at
the address
it
specifies,
pin 12
should be high
when
the chain
is
in
control. Pin 7 of
Z49
goes to the video
RAM
data
buffer.
When
the chain
is
in
control, the
RAM
data
bus should be
disabled.
A
high
on
VRD*
(Video Read) guarantees
this
bus
will
be
off.
We
also find
WR*
and
RD*
tied to pins
14
and
5 of
Z49.
When
the
CPU
takes charge of the video
RAMs,
multiplexer
output
at
pin
12 becomes
VWR*
(Video
Write).
The
CPU
can store data into
the video
RAMs
by
causing
VWR*
to
go
low.
If
the
CPU
wants
to read data
from
video
RAMs, RD*
can
pass
through
Z49
and
activate
VRD*.
A
low
here will
open data buffers
Z60
and Z44. Addressed
video
RAM
data
is
then placed
on
the data bus.
The
CPU
can process
this
data
like
any
other data.
ALPHANUMERIC FORMAT
The
CRT
(Cathode Ray Tube)
in
the display
will
be scanned
twice per second.
The
electronic
beam
in
the
CRT
travels
from top
to
bottom of the screen and
left to right.
Each
screen or
frame consists of
264
scan
lines.
192 scan
lines
are
used
in
the "picture".
72
lines
are
used during
vertical
interval
and
as
upper and lower
boundaries.
Nothing
is
ever
"written"
or visible
within these
72
lines.
There
are
1024
character locations per screen
(or
512,
depending on
status
of
MODESEL).
Each
character
line
consists
of
64
charac-
ters
(or 32,
depending on
the
status
of
MODESEL).
There
are
16 character
lines.
Each
character
line
consists of
12
scan
lines.
An
alphanumeric character
uses
seven scan
lines
while there
are five
blank scan
lines
between character
lines.
We'll
worry about graphics formatting
later.
Part of
Z65
and
Z50
specify the
column
address.
Z32
speci-
fies
the
row
(or
character
line).
Z12
specifies
the scan
line
in
any
character
line.
The
outputs
from
Z12
are
labeled L1,
L2,
L4 and
L8.
These four
lines
are
not used
in
video
RAM
addressing because
we
already stated
a
row and column
address
will
specify
any one
of the
1024
rectangles
in
our
rectangle array.
Z12's outputs
are
used
in
the video proces-
sing.
L1, L2,
and L4
will
enable the character generator
to
output correct data for any character since
it
knows where
the
CRT's
electron
beam
is
scanning.
L8
is
used
by
the
video processor
to
blank (turn
off)
the five lines
between
character
lines.
16