Radio Shack TRS-80 Technical Manual page 22

Delay Blank
(DLY BLANK)
is
tied to
Z26,
pins
1
and
2.
When
high,
this
input
tells
Z26
that the electron
beam
is
indeed
in
the video portion of the screen.
Once
all
conditions
are
met and
LATCH
goes low,
Z26
will
go low. Just
like
Z10, Z1
1
will
load
dot
data;
and
when
pin
15
goes
back
high,
the
shift
process
will
start.
The
six
graphic dots are shifted
out
of pin 13.
Notice pin 9 of
Z1
1
is
pulled
up by R40.
Likewise, pins
3,
2,
1
and 6
are tied to
ground.
But
pin
14
is
used
this
time.
In
graphics,
there
is
not
a
blank dot space between charac-
ter rectangles.
SYNC
GENERATOR
The Sync
Generator circuit
accepts timing
signals
from
the
divider
chain to develop horizontal
and
vertical
sync pulses
for the display.
These pulses are used
by the display to con-
trol the
CRT's
electron
beam.
The
sync
pulses are
generated
by
logic
which
operate
like
linear
elements.
Z6,
a
CMOS
inverter,
is
used
to generate the horizontal
pulse;
and
Z57
is
used to generate the vertical pulse. Signal
HDRV
(Horizontal Drive)
is
sourced
from
the divider chain
at
Z50,
pin 11. This signal
is
buffered
by Z6,
pins 13,
12,
1
and
2,
and applied to
potentiometer R20.
R20
controls
where
the horizontal pulse starts in
reference to
HDRV.
When
R20's wiper
is
close
to Z6, pin
2,
the horizontal
pulse will start
almost
at
the
same
time
as
HDRV
goes
high.
When
the
wiper
is
moved
in
the opposite direction,
there
is
a
delay
between
the time
HDRV
goes high and the
time the horizontal pulse
starts.
R20
is
not performing
this
phase
shift
by
itself.
C20, together with
two
inverters
in
Z6,
form the
complete
shift
network.
Here's
how
it
works:
HDRV
goes high,
causing Z6, pin
2,
to
go high
(in this
case
about
5.0 volts).
A
current flows
through
R20
charging
C20. While
C20
charges, the voltage
at
pin
3
of
Z6
slowly increases
from
zero
as
the current
through
R20
decreases. After
a
length of time, the voltage
at
pin
3
of
Z6
will
be high
enough
for pin
3
to
"see"
a
high.
Z6, pin
4,
goes
low
causing pin 6 to
go
high.
C20
rapidly
charges.
Everything
stays
in
this
mode
until
HDRV
goes
low.
At
this
point,
C20
starts
to discharge
at
the
same
rate
it
charged.
When
the voltage
at
Z6, pin
3,
decreases to
a
logical
"0"
level,
pin
4
will
go high,
causing pin 6
to
go low.
C20
rapidly discharges.
The
process cycle
is
now
complete
until
the
next time
HDRV
goes
high.
The
time the voltage
level
at pin
3 of
Z6
stays
above the
minimum
logical
"1"
level
determines the
amount
of shift
from
HDRV. The
effect of
R20's
position,
which
adjusts the delay time,
on
the screen
is
a
horizontal
shift
of video
display.
After the horizontal
signal
is
phase
shifted,
the horizontal
pulse
must
be shaped.
C21 and
R43
form
a
differentiation
network which
creates
a
smaller pulse of
known width from
the shifted
HDRV
signal.
Operation
is
quite simple.
When
Z6, pin
6,
goes high,
C21
and
R43
differentiate the rising
edge.
A
narrow pulse
is
passed to Z6, pin 11, inverted
by
pin
10 and
inverted
and buffered by Z6, pins
9 and
8.
The
next
result
is
a
pulse
about four
microseconds long, called
horizontal sync.
The
vertical
sync phase
shift
operates
in
the exact
same
manner
as
the horizontal.
Z57
is
used
as
the active
element
which R21 and
C26
form the delay network.
The
differen-
tial
network
consists
of
C27
and R44. Notice the only
dif-
ference
between
horizontal
and
vertical circuits
is
the value
of the
two
capacitive devices.
HORIZONTAL
AND
VERTICAL MIXING
Once
the
two
sync
pulses are
phase
shifted
and
pulse-
shaped,
NAND
gate
Z5
is
used
to
mix
the
two
signals
together and
serrate
the
vertical interval.
Figure 8
shows
idealized
waveforms around Z5.
At
line
A, the
horizontal pulses are
shown.
The
source for
this
output
is
Z6,
pin
8.
At
line
B, the vertical
pulse
is
shown coming
from Z57,
pin
8.
Z5,
pins
1
and
2 are tied
to the
waveforms shown
at lines
A
and
B,
and
the resulting
NANDed
output
is
shown
on
line C.
Line
C
in
Figure 8
is
now
used
as a
source to
NAND
the horizontal
and
vertical
syncs
once more.
Line
D
shows
the result of
NANDing
line
C
with
line
A. Line E
shows
the
result
of
NANDing
Line
C
with Line
B.
Lines
D
and E
are
NANDed
by Z5, pins 10
and
9.
The
resulting
mixed
sync
waveshape
is
shown
on
Line
F.
Notice
two
things
about Z5.
First,
pin
8's
output
shown
in
Figure
8,
line F,
is
"false"
composite sync.
In
other words,
it is
inverted
away from
true
form. Secondly,
notice
Z5 may
be evaluated
down
using
Boolean algebra
into
a
2-input exclusive
OR
gate.
The output
at line
C may
be expressed
as
VH
+ HV,
where
V
is
vertical
sync
at
Line
B
and
H
is
horizontal
sync
at line
A
in
Figure
8.
VIDEO MIXING
The
video mixing
circuitry
generates the
composite video
signal for
the
display.
The
video
mixer
accepts
both
alpha-
numeric
or graphics
dot data
from
the
shift register, level-
shifts
it,
and
places
it
atop
the
composite syncs.
The com-
posite
waveform
is
then buffered to drive
a
75
ohm
impe-
dance and
is
sent, via cable,
to the video display.
Dot
data
from
shift register
Z10
or
Z11
is
applied to
Z30,
pin
3 or pin
2.
You
should never
see
both pin
3 and
pin 2
active at
the
same
time.
While
Z10
is
outputting
alpha-
numeric
data,
Z11,
pin 13,
should be low. Conversely,
if
Z11
is
outputting graphic data,
Z10,
pin 13,
should be
low.
The
net result at pin
1,
Z30,
is
a
single
waveshape
of
video dot
data.
This data
is
applied to
Z41,
pins
6 and
7.
20