Table of Contents
Advertisement
G310 Service Manual
4.2.3 Receiver Section
4.2.3.1 An Overview of Receive section
The G310 model's Aero transceiver uses a low-IF receiver architecture that follows for the on-chip
integration of the channel selection filters, eliminating the external RF image reject filters and the IF
SAW filter required in conventional superheterodyne architectures. Compared to a direct
conversion architecture, the low-IF architecture has a much greater degree of immunity to dc
offsets that can arise from RF local oscillator (RFLO) self-mixing, 2
and device 1/f noise. This relaxes the common-mode balance requirements on the input SAW filters
and simplifies PC board design and manufacturing.
The Si4200 integrates three differential-input LNAs( At G310, we only used two inputs that are
EGSM and PCS). The GSM input supports EGSM 900 (925– 960 MHz) band. The PCS input
supports the PCS 1900 (1930 – 1990 MHz).
A quadrature image-reject mixer downconverts the RF signal to a 100 kHz intermediate frequency
(IF) with the RFLO from the Si4133T frequency synthesizer. The RFLO frequency is between
1737.8 and 1989.9 MHz, and is divided by two in the Si4200 for GSM 850 and EGSM 900 modes.
The mixer output is amplified with an analog programmable gain amplifer (PGA), which is controlled
with the AGAIN[2:0] bits in register 05h. The quadrature IF signal is digitized with high resolution
A/D converters (ADCs).
The Si4201 downconverts the ADC output to baseband with a digital 100 kHz quadrature LO signal.
Digital decimation and IIR filters perform channel selection to remove blocking and reference
interference signals. After channel selection, the digital output is scaled with a digital PGA, which is
controlled with the DGAIN[5:0] bits in register 05h.
These analog and digital gain resigters must be set to provide a constant amplitude signal to the
baseband receive inputs.
DACs drive a differential analog signal onto the RXIP,RXIN,RXQP and RXQN pins to interface to
standard analog-input baseband Ics.
Fig.4-6. Receiver block diagram
17
PANTECH
nd
order distortion of blockers,
R&D CONFIDENTIAL
Advertisement
Table of Contents
