Silicon Laboratories EMBER EM358 series Reference Manual
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Silicon Laboratories EMBER EM358 series Reference Manual

Silicon Laboratories EMBER EM358 series Reference Manual

Integrated zigbee/802.15.4 soc
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Ember EM358x
®
E
EM358
R
M
MBER
X
EFERENCE
ANUAL
®
This reference manual accompanies several documents to provide the complete description of Ember
EM358x
devices. In the event that the device data sheet and this document contain conflicting information, the device data
sheet should be considered the authoritative source.
Rev 0.4 8/13
Copyright © 2013 by Silicon Laboratories
EM358x
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

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  • Page 1 In the event that the device data sheet and this document contain conflicting information, the device data sheet should be considered the authoritative source. Rev 0.4 8/13 Copyright © 2013 by Silicon Laboratories EM358x This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
  • Page 2 EM358x Rev. 0.4...

  • Page 3: Table Of Contents

    EM358x ABLE OF ONTENTS Related Documents and Conventions ................8     Related Documents ......................8     1.1.1 EM358x Data Sheet .................... 8     1.1.2 ZigBee Specification ................... 8     1.1.3 ZigBee PRO Stack Profile ................... 8  ...
  • Page 4 EM358x 5.3.1 High-Frequency Internal RC Oscillator (OSCHF) ..........42     5.3.2 High-Frequency Crystal Oscillator (OSC24M) ..........42     5.3.3 Low-Frequency Internal RC Oscillator (OSCRC) ..........43     5.3.4 Low-Frequency Crystal Oscillator (OSC32K) ............ 43     5.3.5 Clock Switching ....................
  • Page 5 EM358x SPI - Slave Mode ......................88     8.4.1 GPIO Usage ...................... 88     8.4.2 Set Up and Configuration .................. 88     8.4.3 Operation ......................89     8.4.4 DMA ........................90     8.4.5 Interrupts ......................90  ...
  • Page 6 EM358x 10.3.5 Input Capture Mode ..................151     10.3.6 PWM Input Mode .................... 152     10.3.7 Forced Output Mode ..................152     10.3.8 Output Compare Mode ..................153     10.3.9 PWM Mode ..................... 154     10.3.10 One-Pulse Mode ....................
  • Page 7 EM358x Rev. 0.4...

  • Page 8: Related Documents And Conventions

    This reference manual accompanies several documents to provide the complete description of the Ember EM358x devices. 1.1.1 EM358x Data Sheet The Silicon Laboratories EM358x data sheet provides the configuration information for the EM358x. 1.1.2 ZigBee Specification The core ZigBee specification (Document 053474) defines ZigBee's smart, cost-effective and energy-efficient mesh network.

  • Page 9: Conventions

    EM358x 1.2 Conventions Abbreviations and acronyms used in this data sheet are explained in Table 1-1. Table 1-1. Acronyms and Abbreviations Acronym/Abbreviation Meaning Acknowledgement Analog to Digital Converter Advanced Encryption Standard Automatic Gain Control Advanced High Speed Bus Advanced Peripheral Bus CBC-MAC Cipher Block Chaining—Message Authentication Code Clear Channel Assessment...
  • Page 10 EM358x Acronym/Abbreviation Meaning Flash Patch and Breakpoint GPIO General Purpose I/O (pins) High Frequency Inter-Integrated Circuit Integrated Development Environment Intermediate Frequency IEEE Institute of Electrical and Electronics Engineers Integral Non-linearity Instrumentation Trace Macrocell JTAG Joint Test Action Group Low Frequency Low Noise Amplifier Link Quality Indicator Least significant bit...
  • Page 11 EM358x Acronym/Abbreviation Meaning PCLK Peripheral clock Packet Error Rate Physical Layer Phase-Locked Loop Power-On-Reset PRNG Pseudo Random Number Generator Power Spectral Density Packet Trace Interface Pulse Width Modulation Quad Flat Pack Random Access Memory Resistive/Capacitive Radio Frequency Root Mean Square RoHS Restriction of Hazardous Substances RSSI...

  • Page 12: Arm ® Cortex™-M3 And Memory Modules

    EM358x ® 2 ARM Cortex™-M3 and Memory Modules ® This chapter discusses the ARM Cortex -M3 Microprocessor, and reviews the EM358x’s flash and RAM memory modules as well as the Memory Protection Unit (MPU). ® 2.1 ARM Cortex™-M3 Microprocessor ® The EM358x integrates the ARM Cortex -M3 microprocessor, revision r1p1, developed by ARM Ltd., making...

  • Page 13: Embedded Memory

    EM358x 2.2 Embedded Memory ® Figure 2-1 shows the EM358x ARM Cortex -M3 memory map. ® Figure 2-1. EM358x ARM Cortex -M3 Memory Map Rev. 0.4...

  • Page 14: Flash Memory

    EM358x 2.2.1 Flash Memory 2.2.1.1 Flash Overview The EM358x provides a total of either 256 or 512 kB of flash memory. The flash memory is provided in three separate blocks:  Main Flash Block (MFB)  Fixed Information Block (FIB) ...
  • Page 15 EM358x Table 2-1. Option Byte Storage Address bits [15:8] bits [7:0] Notes 0x08080800 Inverse Option Byte 0 Option Byte 0 Configures flash read protection 0x08080802 Inverse Option Byte 1 Option Byte 1 Reserved 0x08080804 Inverse Option Byte 2 Option Byte 2 Available for customer use 0x08080806 Inverse Option Byte 3...
  • Page 16 EM358x Option Byte Notes Option Byte 4 bit [0] Write protection of address range 0x08000000 – 0x08003FFF bit [1] Write protection of address range 0x08004000 – 0x08007FFF bit [2] Write protection of address range 0x08008000 – 0x0800BFFF bit [3] Write protection of address range 0x0800C000 – 0x0800FFFF bit [4] Write protection of address range 0x08010000 –...

  • Page 17: Ram

    EM358x 2.2.1.5 Simulated EEPROM Ember software reserves 8 kB of the main flash block as a simulated EEPROM storage area for stack and customer tokens. The simulated EEPROM storage area implements a wear-leveling algorithm to extend the number of simulated EEPROM write cycles beyond the physical limit of 20,000 write cycles for which each flash cell is qualified.

  • Page 18: Memory Protection Unit

    EM358x 2.3 Memory Protection Unit ® The EM358x includes the ARM Cortex -M3 Memory Protection Unit, or MPU. The MPU controls access rights and characteristics of up to eight address regions, each of which may be divided into eight equal sub-regions. ®...

  • Page 19: Interrupt System

    EM358x 3 Interrupt System ® The EM358x’s interrupt system is composed of two parts: a standard ARM Cortex -M3 Nested Vectored Interrupt Controller (NVIC) that provides top-level interrupts, and a proprietary Event Manager (EM) that provides second-level interrupts. The NVIC and EM provide a simple hierarchy. All second-level interrupts from the EM feed into top-level interrupts in the NVIC.
  • Page 20 EM358x Exception Position Description SVCall System service call with SVC instruction. Synchronous. Debug Monitor Debug monitor, when not halting. Synchronous, but only active when enabled. It does not activate if lower priority than the current activation. Reserved. PendSV Pendable request for system service. Asynchronous and only pended by software. SysTick System tick timer has fired.
  • Page 21 EM358x ® The top-level interrupts are controlled through five ARM Cortex -M3 NVIC registers: INT_CFGSET, INT_CFGCLR, INT_PENDSET, INT_PENDCLR, and INT_ACTIVE. Writing 0 into any bit in any of these five register is ineffective.  INT_CFGSET - Writing 1 to a bit in INT_CFGSET enables that top-level interrupt. ...

  • Page 22: Event Manager

    EM358x 3.2 Event Manager ® While the standard ARM Cortex -M3 Nested Vectored Interrupt Controller provides top-level interrupts into the CPU, the proprietary Event Manager provides second-level interrupts. The Event Manager takes a large variety of hardware interrupt sources from the peripherals and merges them into a smaller group of interrupts in the NVIC. Effectively, all second-level interrupts from a peripheral are “OR’d”...
  • Page 23 EM358x The INT_periphFLAG register bits are designed to remain set if the second-level interrupt event re-occurs at the same moment as the INT_periphFLAG register bit is being cleared. This ensures the re-occurring second-level interrupt event is not missed. If another enabled second-level interrupt event of the same type occurs before the first interrupt event is cleared, the second interrupt event is lost because no counting or queuing is used.

  • Page 24: Non-Maskable Interrupt (Nmi)

    EM358x NVIC Interrupt EM Interrupt NVIC Interrupt EM Interrupt (top-level) (second-level) (top-level) (second-level) INT_IRQC INT_SCRXVAL INT_IRQB INT_SLEEPTMR INT_IRQA INT_BB INT_ADC INT_ADCFLAG register INT_MGMT INT_ADCOVF INT_TMR2 INT_TMR2FLAG register INT_ADCSAT INT_TMRTIF INT_ADCULDFULL INT_TMRCC4IF INT_ADCULDHALF INT_TMRCC3IF INT_ADCDATA INT_TMRCC2IF INT_MACRX INT_TMRCC1IF INT_MACTX INT_TMRUIF INT_MACTMR INT_TMR1 INT_TMR1FLAG register INT_SEC...

  • Page 25: Faults

    EM358x 3.4 Faults Four of the exceptions in the NVIC are faults: Hard Fault, Memory Fault, Bus Fault, and Usage Fault. Of these, ® three (Hard Fault, Memory Fault, and Usage Fault) are standard ARM Cortex -M3 exceptions. The Bus Fault, though, is derived from EM358x-specific sources. The Bus Fault sources are recorded in the SCS_AFSR register.

  • Page 26: Registers

    EM358x 3.5 Registers INT_CFGSET Top-Level Set Interrupts Configuration Register Address: 0xE000E100 Reset: 0x0 INT_USB INT_RSVD18 INT_RSVD17 INT_DEBUG INT_IRQD INT_IRQC INT_IRQB INT_IRQA INT_ADC INT_MACRX INT_MACTX INT_MACTMR INT_SEC INT_SC2 INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT INT_TIM2 INT_TIM1 Bitname Bitfield Access Description INT_USB [19] Write 1 to enable USB interrupt. (Writing 0 has no effect.) (where applicable) INT_RSVD18 [18]...
  • Page 27 EM358x INT_CFGCLR Top-Level Clear Interrupts Configuration Register Address: 0xE000E180 Reset: 0x0 INT_USB INT_RSVD18 INT_RSVD17 INT_DEBUG INT_IRQD INT_IRQC INT_IRQB INT_IRQA INT_ADC INT_MACRX INT_MACTX INT_MACTMR INT_SEC INT_SC2 INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT INT_TIM2 INT_TIM1 Bitname Bitfield Access Description INT_USB [19] Write 1 to disable USB interrupt. (Writing 0 has no effect.) (where applicable) INT_RSVD18 [18]...
  • Page 28 EM358x INT_PENDSET Top-Level Set Interrupts Pending Register Address: 0xE000E200 Reset: 0x0 INT_USB INT_RSVD18 INT_RSVD17 INT_DEBUG INT_IRQD INT_IRQC INT_IRQB INT_IRQA INT_ADC INT_MACRX INT_MACTX INT_MACTMR INT_SEC INT_SC2 INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT INT_TIM2 INT_TIM1 Bitname Bitfield Access Description INT_USB [19] Write 1 to pend USB interrupt. (Writing 0 has no effect.) (where applicable) INT_RSVD18 [18] Reserved: this bit should be ignored.
  • Page 29 EM358x INT_PENDCLR Top-Level Clear Interrupts Pending Register Address: 0xE000E280 Reset: 0x0 INT_USB INT_RSVD18 INT_RSVD17 INT_DEBUG INT_IRQD INT_IRQC INT_IRQB INT_IRQA INT_ADC INT_MACRX INT_MACTX INT_MACTMR INT_SEC INT_SC2 INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT INT_TIM2 INT_TIM1 Bitname Bitfield Access Description INT_USB [19] Write 1 to unpend USB interrupt. (Writing 0 has no effect.) (where applicable) INT_RSVD18 [18]...
  • Page 30 EM358x INT_ACTIVE Top-Level Active Interrupts Register Address: 0xE000E300 Reset: 0x0 INT_USB INT_RSVD18 INT_RSVD17 INT_DEBUG INT_IRQD INT_IRQC INT_IRQB INT_IRQA INT_ADC INT_MACRX INT_MACTX INT_MACTMR INT_SEC INT_SC2 INT_SC1 INT_SLEEPTMR INT_BB INT_MGMT INT_TIM2 INT_TIM1 Bitname Bitfield Access Description INT_USB [19] USB interrupt active (where applicable) INT_RSVD18 [18] Reserved: this bit should be ignored.
  • Page 31 EM358x INT_MISS Top-Level Missed Interrupts Register Address: 0x4000A820 Reset: 0x0 INT_MISSUSB INT_RSVD18 INT_RSVD17 INT_MISSIRQD INT_MISSIRQC INT_MISSIRQB INT_MISSIRQA INT_MISSADC INT_MISSMACRX INT_MISSMACTX INT_MISSMACTMR INT_MISSSEC INT_MISSSC2 INT_MISSSC1 INT_MISSSLEEP INT_MISSBB INT_MISSMGMT Bitname Bitfield Access Description INT_MISSUSB [19] USB interrupt missed (where applicable) INT_RSVD18 [18] Reserved: this bit should be ignored.
  • Page 32 EM358x SCS_AFSR Auxiliary Fault Status Register Address: 0xE000ED3C Reset: 0x0 WRONGSIZE PROTECTED RESERVED MISSED Bitname Bitfield Access Description WRONGSIZE A bus fault resulted from an 8-bit or 16-bit read or write of an APB peripheral register. This fault can also result from an unaligned 32-bit access.

  • Page 33: Radio Module

    EM358x 4 Radio Module The radio module consists of an analog front end and digital baseband as shown in Figure 4-1. Figure 4-1. EM358 Block Diagram 4.1 Receive (Rx) Path The Rx path uses a low-IF, super-heterodyne receiver that rejects the image frequency using complex mixing and polyphase filtering.

  • Page 34: Rssi And Cca

    EM358x 4.1.2 RSSI and CCA The EM358x calculates the RSSI over every 8-symbol period as well as at the end of a received packet. The linear range of RSSI is specified to be at least 40 dB over temperature. At room temperature, the linear range is approximately 60 dB (-90 dBm to -30 dBm input signal).

  • Page 35: Packet Trace Interface (Pti)

    EM358x  Time stamping received and transmitted messages  Attaching packet information to received packets (LQI, RSSI, gain, time stamp, and packet status)  IEEE 802.15.4-2003 timing and slotted/unslotted timing 4.5 Packet Trace Interface (PTI) The EM358x integrates a true PHY-level PTI for effective network-level debugging. It monitors all the PHY Tx and Rx packets between the MAC and baseband modules without affecting their normal operation.

  • Page 36: System Modules

    EM358x 5 System Modules System modules encompass power domains, resets, clocks, system timers, power management, and encryption. Figure 5-1 shows these modules and how they interact. OSCRC CLK1K DIV10 OSC32A OSC32B CLK32K OSC32K Wakeup Recording deep sleep REG_EN wakeup Power Management watchdog Sleep Timer Watchdog...

  • Page 37: Power Domains

    EM358x 5.1 Power domains The EM358x contains three power domains:  An “always-on domain” containing all logic and analog cells required to manage the EM358x’s power modes, including the GPIO controller and sleep timer. This domain must remain powered.  A “core domain”...
  • Page 38 EM358x Table 5-1. POR HV Thresholds Parameter Test conditions Unit Always-on domain release 0.62 0.95 1.20 Always-on domain assert 0.45 0.65 0.85 Supply rise time From 0.5 V to 1.7 V µs Table 5-2. POR LVcore Thresholds Parameter Test conditions Unit 1.25 V domain release 1.25 V domain assert...

  • Page 39: Reset Recording

    EM358x If an option byte error is detected, the system restarts and the read and check process is repeated. If the error is detected again the process is repeated but stops on the 3 failure. The system is then placed into an emulated deep sleep where recovery is possible.

  • Page 40: Clocks

    EM358x Table 5-5 shows which reset sources generate certain resets. Table 5-5. Generated Resets Reset Source Reset Generation Module Output PORESET SYSRESET DAPRESET PRESET PRESET POR HV POR LV (due to waking from normal deep sleep) POR LV (not due to waking from normal deep sleep) nRESET Watchdog...
  • Page 41 EM358x Figure 5-2 shows a block diagram of the clocks in the EM358x. This simplified view shows all the clock sources and the general areas of the chip to which they are routed. Figure 5-2. Clocks Block Diagram Rev. 0.4...

  • Page 42: High-Frequency Internal Rc Oscillator (Oschf)

    EM358x 5.3.1 High-Frequency Internal RC Oscillator (OSCHF) The high-frequency RC oscillator (OSCHF) is used as the default system clock source when power is applied to the core domain. The nominal frequency coming out of reset is 12 MHz and Ember software calibrates this clock to 12 MHz.

  • Page 43: Low-Frequency Internal Rc Oscillator (Oscrc)

    EM358x Parameter Test conditions Unit Crystal with high ESR Ω Load capacitance Crystal capacitance Crystal power dissipation µW Crystal with low ESR Ω Load capacitance Crystal capacitance Crystal power dissipation 5.3.3 Low-Frequency Internal RC Oscillator (OSCRC) A low-frequency RC oscillator (OSCRC) is provided as an internal timing reference. The nominal frequency coming out of reset is 10 kHz, and Ember software calibrates this clock to 10 kHz.

  • Page 44: Clock Switching

    EM358x Parameter Test conditions Unit Crystal ESR kΩ Start-up time Current consumption At 25°C, VDD_PADS=3.0 V μA 5.3.5 Clock Switching The EM358x has two switching mechanisms for the main system clock, providing four clock modes. Table 5-10 shows these clock modes and how they affect the internal clocks. The register bit OSC24M_CTRL_OSC24M_SEL in the OSC24M_CTRL register switches between the high- frequency RC oscillator (OSCHF) and the high-frequency crystal oscillator (OSC24M) as the main system clock (SYSCLK).

  • Page 45: Sleep Timer

    EM358x 5.4.2 Sleep Timer The EM358x integrates a 32-bit timer dedicated to system timing and waking from sleep at specific times. The sleep timer can use either the calibrated 1 kHz reference (CLK1K), or the 32 kHz crystal clock (CLK32K). The default clock source is the internal 1 kHz clock.
  • Page 46 EM358x  Wake on serial controller 1: Wake due to a change of state on GPIO Pin PB2.  Wake on serial controller 2: Wake due to a change of state on GPIO Pin PA2.  Wake on IRQD: Wake due to a change of state on IRQD. Since IRQD can be configured to point to any GPIO, this wake source is another means of waking on any GPIO activity.

  • Page 47: Basic Sleep Modes

    EM358x 5.5.2 Basic Sleep Modes The power management state diagram in Figure 5-3 shows the basic operation of the power management controller. CDBGPWRUPREQ set EMULATED DEEP SLEEP DEEP SLEEP CDBGPWRUPREQ cleared Deep sleep requested (WFI instruction with SLEEP_DEEP=1) PRE-DEEP RUNNING SLEEP IDLE SLEEP Figure 5-3.

  • Page 48: Ram Retention In Deep Sleep

    EM358x To conserver power, OSCRC can be turned of during deep sleep. This mode is known as deep sleep 2. Since the OSCRC is disabled, the sleep timer and watchdog timer do not function and cannot wake the chip unless the low- frequency 32.768 kHz crystal oscillator is used.

  • Page 49: Registers

    EM358x 5.5.6 Registers RAM_RETAIN RAM Retention Register Address: 0x4000403C Reset: 0xFFFF RETAIN RETAIN Bitname Bitfield Access Description RETAIN [15] Sets the retention option for 0x2000F000 to 0x2000FFFF RETAIN [14] Sets the retention option for 0x2000E000 to 0x2000EFFF RETAIN [13] Sets the retention option for 0x2000D000 to 0x2000DFFF RETAIN [12] Sets the retention option for 0x2000C000 to 0x2000CFFF...

  • Page 50: Security Accelerator

    EM358x PERIPHERAL_DISABLE Peripheral Disable Register Address: 0x40004038 Reset: 0x0 PERIDIS_USB PERIDIS_ PERIDIS_ PERIDIS_RSVD PERIDIS_ADC PERIDIS_TIM2 PERIDIS_TIM1 PERIDIS_SC1 PERIDIS_SC2 RSVD7 RSVD6 Bitname Bitfield Access Description PERIDIS_USB Disable the clock to the USB peripheral PERIDIS_RSVD7 Reserved: This bit must be set to 1. PERIDIS_RSVD6 Reserved: This bit must be set to 1.

  • Page 51: Integrated Voltage Regulator

    EM358 6 Integrated Voltage Regulator The EM358x integrates two low dropout regulators to provide 1.8 V and 1.25 V power supplies, as detailed in Table 6-1. The 1V8 regulator supplies the analog and memories, and the 1V25 regulator supplies the digital core. In deep sleep the voltage regulators are disabled.

  • Page 52: Gpio (General Purpose Input / Output)

    EM358x 7 GPIO (General Purpose Input / Output) The EM358x has 24 multi-purpose GPIO pins, which may be individually configured as:  General purpose output  General purpose open-drain output  Alternate output controlled by a peripheral device  Alternate open-drain output controlled by a peripheral device ...

  • Page 53: Configuration

    EM358x  GPIO_PxCLR (clear output data register) clears bits in GPIO_PxOUT.  GPIO_PxSET (set output data register) sets bits in GPIO_PxOUT.  GPIO_PxWAKE (wake monitor register) specifies the pins that can wake the EM358x. In addition to these registers, each port has a pair of configuration registers, GPIO_PxCFGH and GPIO_PxCFGL. These registers specify the basic operating mode for the port’s pins.

  • Page 54: Forced Functions

    EM358x Table 7-2. Timer 2 Output Configuration Controls Timer 2 Output Option Register Bit GPIO Mapping Selected by TIM2_OR Bit TIM2C1 TIM2_OR[4] TIM2C2 TIM2_OR[5] TIM2C3 TIM2_OR[6] TIM2C4 TIM2_OR[7] For outputs assigned to the serial controllers, the serial interface mode registers (SCx_MODE) determine how the GPIO pins are used.

  • Page 55: Reset

    EM358x Disabling all debug functionality prevents external debug tools from operating, including flash programming Note: and high-level debug tools. Disabling the entire SWJ debugger interface is accomplished by setting the GPIO_DEBUGDIS bit in the GPIO_DBGCFG register and not having GPIO PC4 configured in SWDIO mode. In this configuration all debugger-related pins (PC0, PC2, PC3, PC4) behave as standard GPIOs.

  • Page 56: Gpio Modes

    EM358x Figure 7-2. nBOOTMODE and nRESET Timing Timing for a power-on-reset is similar except that OSCHF does not begin oscillating until up to 70 µsec after both core and HV supplies are valid. Combined with the maximum 250 µsec allowed for HV to ramp from 0.5 V to 1.7 V, an additional 320 µsec may be added to the 512 OSCHF clocks until nBOOTMODE is sampled.

  • Page 57: Swdio Mode

    EM358x When configured in input mode:  The output drivers are disabled.  An internal pull-up or pull-down resistor may be activated depending on GPIO_PxCFGH/L and GPIO_PxOUT.  The Schmitt trigger input is connected to the pin.  Reading GPIO_PxIN returns the input at the pin. ...

  • Page 58: Wake Monitoring

    EM358x states the pin when the SPI slave select signal, PB4 (SC1nSSEL) or PA3 (SC2nSSEL), respectively, is deasserted (goes high). When the SPI slave select signal is asserted (low), this pin functions as an alternate push-pull output. 7.7 Wake Monitoring The GPIO_PxWAKE registers specify which GPIOs are monitored to wake the processor.

  • Page 59: Debug Control And Status

    EM358x Two of the four external interrupts, IRQA and IRQB, have fixed pin assignments. The other two external interrupts, IRQC and IRQD, can use any GPIO pin. The GPIO_IRQCSEL and GPIO_IRQDSEL registers specify the GPIO pins assigned to IRQC and IRQD, respectively. Table 7-4 shows how the GPIO_IRQCSEL and GPIO_IRQDSEL register values select the GPIO pin used for the external interrupt.
  • Page 60 EM358x Table 7-5. GPIO Signal Assignments GPIO Analog Alternate Output Input Output Current Drive USBDM TIM2C1 , SC2MOSI TIM2C1 , SC2MOSI Standard USBDP TIM2C3 , SC2MISO, SC2SDA TIM2C3 , SC2MISO, SC2SDA Standard TIM2C4 , SC2SCLK, SC2SCL TIM2C4 , SC2SCLK Standard TIM2C2 TIM2C2 , SC2nSSEL...

  • Page 61: Registers

    EM358x 7.11 Registers GPIO_PxCFGL GPIO_PACFGL Port A Configuration Register (Low) Address: 0x4000B000 Reset: 0x4444 GPIO_PBCFGL Port B Configuration Register (Low) Address: 0x4000B200 Reset: 0x4444 GPIO_PCCFGL Port C Configuration Register (Low) Address: 0x4000B400 Reset: 0x4444 Substitute A, B, or C for x in the following detail description. Px3_CFG Px2_CFG Px1_CFG...
  • Page 62 EM358x GPIO_PxCFGH GPIO_PACFGH Port A Configuration Register (High) Address: 0x4000B004 Reset: 0x4444 GPIO_PBCFGH Port B Configuration Register (High) Address: 0x4000B204 Reset: 0x4444 GPIO_PCCFGH Port C Configuration Register (High) Address: 0x4000B404 Reset: 0x4444 Substitute A, B, or C for x in the following detail description. Px7_CFG Px6_CFG Px5_CFG...
  • Page 63 EM358x GPIO_PxIN GPIO_PAIN Port A Input Data Register Address: 0x4000B008 Reset: 0x0 GPIO_PBIN Port B Input Data Register Address: 0x4000B208 Reset: 0x0 GPIO_PCIN Port C Input Data Register Address: 0x4000B408 Reset: 0x0 Substitute A, B, or C for x in the following detail description. Bitname Bitfield Access...
  • Page 64 EM358x GPIO_PxOUT GPIO_PAOUT Port A Output Data Register Address: 0x4000B00C Reset: 0x0 GPIO_PBOUT Port B Output Data Register Address: 0x4000B20C Reset: 0x0 GPIO_PCOUT Port C Output Data Register Address: 0x4000B40C Reset: 0x0 Substitute A, B, or C for x in the following detail description. Bitname Bitfield Access...
  • Page 65 EM358x GPIO_PxCLR GPIO_PACLR Port A Output Clear Register Address: 0x4000B014 Reset: 0x0 GPIO_PBCLR Port B Output Clear Register Address: 0x4000B214 Reset: 0x0 GPIO_PCCLR Port C Output Clear Register Address: 0x4000B414 Reset: 0x0 Substitute A, B, or C for x in the following detail description. Bitname Bitfield Access...
  • Page 66 EM358x GPIO_PxSET GPIO_PASET Port A Output Set Register Address: 0x4000B010 Reset: 0x0 GPIO_PBSET Port B Output Set Register Address: 0x4000B210 Reset: 0x0 GPIO_PCSET Port C Output Set Register Address: 0x4000B410 Reset: 0x0 Substitute A, B, or C for x in the following detail description. GPIO_PXSETRSVD Bitname Bitfield...
  • Page 67 EM358x GPIO_PxWAKE GPIO_PAWAKE Port A Wakeup Monitor Register Address: 0x4000BC08 Reset: 0x0 GPIO_PBWAKE Port B Wakeup Monitor Register Address: 0x4000BC0C Reset: 0x0 GPIO_PCWAKE Port C Wakeup Monitor Register Address: 0x4000BC10 Reset: 0x0 Substitute A, B, or C for x in the following detail description. Bitname Bitfield Access...
  • Page 68 EM358x GPIO_WAKEFILT GPIO Wakeup Filtering Register Address: 0x4000BC28 Reset: 0x0 IRQD_WAKE_FILTER SC2_WAKE_FILTER SC1_WAKE_FILTER GPIO_WAKE_FILTER Bitname Bitfield Access Description IRQD_WAKE_FILTER Enable filter on GPIO wakeup source IRQD. SC2_WAKE_FILTER Enable filter on GPIO wakeup source SC2 (PA2). SC1_WAKE_FILTER Enable filter on GPIO wakeup source SC1 (PB2). GPIO_WAKE_FILTER Enable filter on GPIO wakeup sources enabled by the GPIO_PnWAKE registers.
  • Page 69 EM358x GPIO_IRQxSEL GPIO_IRQCSEL Interrupt C Select Register Address: 0x4000BC20 Reset: 0xF GPIO_IRQDSEL Interrupt D Select Register Address: 0x4000BC24 Reset: 0x10 Substitute C or D in the detailed description below. SEL_GPIO Bitname Bitfield Access Description SEL_GPIO [4:0] Pin assigned to IRQx. 0x00: PA0.
  • Page 70 EM358x GPIO_INTCFGx GPIO_INTCFGA GPIO Interrupt A Configuration Register Address: 0x4000A860 Reset: 0x0 GPIO_INTCFGB GPIO Interrupt B Configuration Register Address: 0x4000A864 Reset: 0x0 GPIO_INTCFGC GPIO Interrupt C Configuration Register Address: 0x4000A868 Reset: 0x0 GPIO_INTCFGD GPIO Interrupt D Configuration Register Address: 0x4000A86C Reset: 0x0 Substitute A, B, C, or D for x in the following detail description.
  • Page 71 EM358x INT_GPIOFLAG GPIO Interrupt Flag Register Address: 0x4000A814 Reset: 0x0 INT_IRQDFLAG INT_IRQCFLAG INT_IRQBFLAG INT_IRQAFLAG Bitname Bitfield Access Description INT_IRQDFLAG IRQD interrupt pending. Write 1 to clear IRQD interrupt (writing 0 has no effect). INT_IRQCFLAG IRQC interrupt pending. Write 1 to clear IRQC interrupt (writing 0 has no effect).
  • Page 72 EM358x GPIO_DBGCFG GPIO Debug Configuration Register Address: 0x4000BC00 Reset: 0x10 GPIO_DEBUGDIS GPIO_EXTREGEN GPIO_DBGCFGRSVD Bitname Bitfield Access Description GPIO_DEBUGDIS Disable debug interface override of normal GPIO configuration. Configuring PC4 in SWDIO mode will retain the Serial Wire SWDIO functionality. 0: Permit debug interface to be active. 1: Disable debug interface (if it is not already active).
  • Page 73 EM358x GPIO_DBGSTAT GPIO Debug Status Register Address: 0x4000BC04 Reset: 0x0 GPIO_BOOTMODE GPIO_FORCEDBG GPIO_SWEN Bitname Bitfield Access Description GPIO_BOOTMODE The state of the nBOOTMODE signal sampled at the end of reset. 0: nBOOTMODE was not asserted (it read high). 1: nBOOTMODE was asserted (it read low). GPIO_FORCEDBG Status of debugger interface.

  • Page 74: Serial Controllers

    EM358x 8 Serial Controllers 8.1 Overview The EM358x has two serial controllers, SC1 and SC2, which provide several options for full-duplex synchronous and asynchronous serial communications.  SPI (Serial Peripheral Interface), master or slave  TWI (Two Wire serial Interface), master only ...

  • Page 75: Configuration

    EM358x 8.2 Configuration Before using a serial controller, configure and initialize it as follows:  Set up the parameters specific to the operating mode (master/slave for SPI, baud rate for UART, etc.).  Configure the GPIO pins used by the serial controller as shown in Table 8-1 and Table 8-2. Section 2 in Chapter 7, GPIO shows how to configure GPIO pins.

  • Page 76: Registers

    EM358x 8.2.1 Registers SCx_MODE SC1_MODE Serial Mode Register Address: 0x4000C854 Reset: 0x0 SC2_MODE Serial Mode Register Address: 0x4000C054 Reset: 0x0 SC_MODE Bitname Bitfield Access Description SC_MODE [1:0] Serial controller mode. 0: Disabled. 1: UART mode (valid only for SC1). 2: SPI mode. 3: TWI mode.
  • Page 77 EM358x INT_SCxFLAG INT_SC1FLAG Serial Controller 1 Interrupt Flag Register Address: 0x4000A808 Reset: 0x0 INT_SC2FLAG Serial Controller 2 Interrupt Flag Register Address: 0x4000A80C Reset: 0x0 INT_SC1PARERR INT_SC1FRMERR INT_SCTXULDB INT_SCTXULDA INT_SCRXULDB INT_SCRXULDA INT_SCNAK INT_SCCMDFIN INT_SCTXFIN INT_SCRXFIN INT_SCTXUND INT_SCRXOVF INT_SCTXIDLE INT_SCTXFREE INT_SCRXVAL Bitname Bitfield Access Description...
  • Page 78 EM358x INT_SCxCFG INT_SC1CFG Serial Controller 1 Interrupt Configuration Register Address: 0x4000A848 Reset: 0x0 INT_SC2CFG Serial Controller 2 Interrupt Configuration Register Address: 0x4000A84C Reset: 0x0 INT_SC1PARERR INT_SC1FRMERR INT_SCTXULDB INT_SCTXULDA INT_SCRXULDB INT_SCRXULDA INT_SCNAK INT_SCCMDFIN INT_SCTXFIN INT_SCRXFIN INT_SCTXUND INT_SCRXOVF INT_SCTXIDLE INT_SCTXFREE INT_SCRXVAL Bitname Bitfield Access Description...
  • Page 79 EM358x SCx_INTMODE SC1_INTMODE Serial Controller 1 Interrupt Mode Register Address: 0x4000A854 Reset: 0x0 SC2_INTMODE Serial Controller 2 Interrupt Mode Register Address: 0x4000A858 Reset: 0x0 SC_TXIDLELEVEL SC_TXFREELEVEL SC_RXVALLEVEL Bitname Bitfield Access Description SC_TXIDLELEVEL Transmitter idle interrupt mode - 0: edge triggered, 1: level triggered. SC_TXFREELEVEL Transmit buffer free interrupt mode - 0: edge triggered, 1: level triggered.

  • Page 80: Spi - Master Mode

    EM358x 8.3 SPI - Master Mode The SPI master controller has the following features:  Full duplex operation  Programmable clock frequency (12 MHz max.)  Programmable clock polarity and phase  Selectable data shift direction (either LSB or MSB first) ...

  • Page 81: Operation

    EM358x Table 8-4. SPI Master Mode Formats SCx_SPICFG SC_SPIxxx PHA POL Frame Formats Same as above except data is sent LSB first instead of MSB first The notation xxx means that the corresponding column header below is inserted to form the field name. 8.3.3 Operation Characters transmitted and received by the SPI master controller are buffered in transmit and receive FIFOs that...

  • Page 82: Interrupts

    EM358x the transmit serializer is idle, indicated by a cleared SC_SPITXIDLE bit in the SCx_SPISTAT register. Refer to the register description of SCx_SPICFG for more detailed information about SC_SPIRPT. Every time an automatic character transmission starts, a transmit underrun is detected as there is no data in transmit FIFO, and the INT_SCTXUND bit in the INT_SC2FLAG register is set.

  • Page 83: Registers

    EM358x 8.3.5 Registers SCx_DATA SC1_DATA Serial Data Register Address: 0x4000C83C Reset: 0x0 SC2_DATA Serial Data Register Address: 0x4000C03C Reset: 0x0 SC_DATA Bitname Bitfield Access Description SC_DATA [7:0] Transmit and receive data register. Writing to this register adds a byte to the transmit FIFO.
  • Page 84 EM358x SCx_SPICFG SC1_SPICFG SPI Configuration Register Address: 0x4000C858 Reset: 0x0 SC2_SPICFG SPI Configuration Register Address: 0x4000C058 Reset: 0x0 SC_SPIRXDRV SC_SPIMST SC_SPIRPT SC_SPIORD SC_SPIPHA SC_SPIPOL Bitname Bitfield Access Description SC_SPIRXDRV Receiver-driven mode selection bit (SPI master mode only). Clear this bit to initiate transactions when transmit data is available.
  • Page 85 EM358x SCx_SPISTAT SC1_SPISTAT SPI Status Register Address: 0x4000C840 Reset: 0x0 SC2_SPISTAT SPI Status Register Address: 0x4000C040 Reset: 0x0 SC_SPITXIDLE SC_SPITXFREE SC_SPIRXVAL SC_SPIRXOVF Bitname Bitfield Access Description SC_SPITXIDLE This bit is set when both the transmit FIFO and the transmit serializer are empty.
  • Page 86 EM358x SCx_RATELIN SC1_RATELIN Serial Clock Linear Prescaler Register Address: 0x4000C860 Reset: 0x0 SC2_RATELIN Serial Clock Linear Prescaler Register Address: 0x4000C060 Reset: 0x0 SC_RATELIN Bitname Bitfield Access Description SC_RATELIN [3:0] The linear component (LIN) of the clock rate in the equation: rate = 12MHz / ( (LIN + 1) * (2^EXP) ) Rev.
  • Page 87 EM358x SCx_RATEEXP SC1_RATEEXP Serial Clock Exponential Prescaler Register Address: 0x4000C864 Reset: 0x0 SC2_RATEEXP Serial Clock Exponential Prescaler Register Address: 0x4000C064 Reset: 0x0 SC_RATEEXP Bitname Bitfield Access Description SC_RATEEXP [3:0] The exponential component (EXP) of the clock rate in the equation: rate = 12MHz / ( (LIN + 1) * (2^EXP) ) Rev.

  • Page 88: Spi - Slave Mode

    EM358x 8.4 SPI - Slave Mode Both SC1 and SC2 SPI controllers include a SPI slave controller with these features:  Full duplex operation  Up to 5 Mbps data transfer rate  Programmable clock polarity and clock phase  Selectable data shift direction (either LSB or MSB first) ...

  • Page 89: Operation

    EM358x The SPI slave controller supports various frame formats depending upon the clock polarity (SC_SPIPOL), clock phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see Table 8-6). The SC_SPIPOL, SC_SPIPHA, and SC_SPIORD bits are defined within the SCx_SPICFG registers. Table 8-6. SPI Slave Formats SCx_SPICFG SC_SPIxxx MST ORD PHA POL...

  • Page 90: Dma

    EM358x indication: setting the appropriate SC_TX/RXDMARST bit in the SCx_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded. Receiving a character causes the serial transmission of a character pulled from the transmit FIFO. When the transmit FIFO is empty, a transmit underrun is detected (no data in transmit FIFO) and the INT_SCTXUND bit in the INT_SCxFLAG register is set.

  • Page 91: Gpio Usage

    EM358x  Compatible with Philips’ I C-bus slave devices 8.5.1 GPIO Usage The TWI master controller uses just two signals:  SDA (Serial Data) – bidirectional serial data  SCL (Serial Clock) – bidirectional serial clock Table 8-7 lists the GPIO pins used by the SC1 and SC2 TWI master controllers. Because the pins are configured as open-drain outputs, they require external pull-up resistors.
  • Page 92 EM358x Table 8-9. TWI Master Frame Segments SCx_TWICTRL1 SC_TWIxxxx START SEND RECV STOP Frame Segments TWI stop segment - after frame with NACK or stop outSLAVE outSLAVE No pending frame segment Illegal The notation xxx means that the corresponding column header below is inserted to form the field name. Full TWI frames have to be constructed by software from individual TWI segments.

  • Page 93: Interrupts

    EM358x IDLE START Segment STOP Segment TRANSMIT Segment received ACK ? RECEIVE Segment RECEIVE Segment with NACK with ACK Figure 8-2. TWI Segment Transitions Generation of a 7-bit address is accomplished with one transmit segment. The upper 7 bits of the transmitted character contain the 7-bit address.

  • Page 94: Registers

    EM358x 8.5.5 Registers Refer to Registers (in the SPI Master Mode section) for a description of the SCx_DATA, SCx_RATELIN, and SCx_RATEEXP registers. SCx_TWISTAT SC1_TWISTAT TWI Status Register Address: 0x4000C844 Reset: 0x0 SC2_TWISTAT TWI Status Register Address: 0x4000C044 Reset: 0x0 SC_TWICMDFIN SC_TWIRXFIN SC_TWITXFIN SC_TWIRXNAK Bitname Bitfield...
  • Page 95 EM358x SCx_TWICTRL1 SC1_TWICTRL1 TWI Control Register 1 Address: 0x4000C84C Reset: 0x0 SC2_TWICTRL1 TWI Control Register 1 Address: 0x4000C04C Reset: 0x0 SC_TWISTOP SC_TWISTART SC_TWISEND SC_TWIRECV Bitname Bitfield Access Description SC_TWISTOP Setting this bit sends the STOP command. It clears when the command completes.
  • Page 96 EM358x SCx_TWICTRL2 SC1_TWICTRL2 TWI Control Register 2 Address: 0x4000C850 Reset: 0x0 SC2_TWICTRL2 TWI Control Register 2 Address: 0x4000C050 Reset: 0x0 SC_TWIACK Bitname Bitfield Access Description SC_TWIACK Setting this bit signals ACK after a received byte. Clearing this bit signals NACK after a received byte. Rev.

  • Page 97: Uart - Universal Asynchronous Receiver / Transmitter

    EM358x 8.6 UART - Universal Asynchronous Receiver / Transmitter The SC1 UART is enabled by writing 1 to SC1_MODE. The SC2 serial controller does not include UART functions. The UART supports the following features:  Flexible baud rate clock (300 bps to 921.6 kbps) ...
  • Page 98 EM358x Table 8-11. UART Baud Rate Divisors for Common Baud Rates Baud Rate SC1_UARTPER SC1_UARTFRAC Baud Rate Error (%) (bits/sec) 40000 2400 5000 4800 2500 9600 1250 19200 38400 57600 - 0.08 115200 + 0.16 230400 + 0.16 460800 + 0.16 921600 + 0.16 The UART can miss bytes when the inter-byte gap is long or there is a baud rate mismatch between receiver and...

  • Page 99: Fifos

    EM358x  SC_UARTODD specifies whether transmitted and received parity bits contain odd or even parity. If this bit is clear, the parity bit is even, and if set, the parity bit is odd. Even parity is the exclusive-or of all of the data bits, and odd parity is the inverse of the even parity value.

  • Page 100: Dma

    EM358x Figure 8-5. RTS/CTS Flow Control Connections The UART RTS/CTS flow control options are selected by the SC_UARTFLOW and SC_UARTAUTO bits in the SC1_UARTCFG register (see Table 8-12). Whenever the SC_UARTFLOW bit is set, the UART will not start transmitting a character unless nCTS is low (asserted). If nCTS transitions to the high state (deasserts) while a character is being transmitted, transmission of that character continues until it is complete.
  • Page 101 EM358x  Receive FIFO changed from empty to not empty (depending on SCx_INTMODE, either the 0 to 1 transition or the high level of SC_UARTRXVAL)  Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)  Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B) ...

  • Page 102: Registers

    EM358x 8.6.7 Registers Refer to Registers (in the SPI Master Mode section) for a description of the SCx_DATA register. SC1_UARTSTAT UART Status Register Address: 0x4000C848 Reset: 0x40 SC_UARTTXIDLE SC_UARTPARERR SC_UARTFRMERR SC_UARTRXOVF SC_UARTTXFREE SC_UARTRXVAL SC_UARTCTS Bitname Bitfield Access Description SC_UARTTXIDLE This bit is set when both the transmit FIFO and the transmit serializer are empty.
  • Page 103 EM358x SC1_UARTCFG UART Configuration Register Address: 0x4000C85C Reset: 0x0 SC_UARTAUTO SC_UARTFLOW SC_UARTODD SC_UARTPAR SC_UART2STP SC_UART8BIT SC_UARTRTS Bitname Bitfield Access Description SC_UARTAUTO Set this bit to enable automatic nRTS control by hardware (SC_UARTFLOW must also be set). When automatic control is enabled, nRTS will be deasserted when the receive FIFO has space for only one more byte (inhibits transmission from the other device) and will be asserted if it has space for more than one byte (enables transmission from...
  • Page 104 EM358x SC1_UARTPER UART Baud Rate Period Register Address: 0x4000C868 Reset: 0x0 SC_UARTPER SC_UARTPER Bitname Bitfield Access Description SC_UARTPER [15:0] The integer part of baud rate period (N) in the equation: rate = 24MHz / ( (2 * N) + F ) Rev.
  • Page 105 EM358x SC1_UARTFRAC UART Baud Rate Fractional Period Register Address: 0x4000C86C Reset: 0x0 SC_UARTFRAC Bitname Bitfield Access Description SC_UARTFRAC The fractional part of the baud rate period (F) in the equation: rate = 24MHz / ( (2 * N) + F ) Rev.

  • Page 106: Dma Channels

    EM358x 8.7 DMA Channels The EM358x serial DMA channels enable efficient, high-speed operation of the SPI and UART controllers by reducing the load on the CPU as well as decreasing the frequency of interrupts that it must service. The transmit and receive DMA channels can transfer data between the transmit and receive FIFOs and the DMA buffers in main memory as quickly as it can be transmitted or received.

  • Page 107: Registers

    EM358x 8.7.1 Registers SCx_DMACTRL SC1_DMACTRL Serial DMA Control Register Address: 0x4000C830 Reset: 0x0 SC2_DMACTRL Serial DMA Control Register Address: 0x4000C030 Reset: 0x0 SC_TXDMARST SC_RXDMARST SC_TXLODB SC_TXLODA SC_RXLODB SC_RXLODA Bitname Bitfield Access Description SC_TXDMARST Setting this bit resets the transmit DMA. The bit clears automatically. SC_RXDMARST Setting this bit resets the receive DMA.
  • Page 108 EM358x SCx_DMASTAT SC1_DMASTAT Serial DMA Status Register Address: 0x4000C82C Reset: 0x0 SC2_DMASTAT Serial DMA Status Register Address: 0x4000C02C Reset: 0x0 SC_RXSSEL SC_RXFRMB SC_RXFRMA SC_RXPARB SC_RXPARA SC_RXOVFB SC_RXOVFA SC_TXACTB SC_TXACTA SC_RXACTB SC_RXACTA Bitname Bitfield Access Description SC_RXSSEL [12:10] Status of the receive count saved in SCx_RXCNTSAVED (SPI slave mode) when nSSEL deasserts.
  • Page 109 EM358x Bitname Bitfield Access Description SC_RXOVFA This bit is set when DMA receive buffer A was passed an overrun error from the receive FIFO. Neither receive buffer was capable of accepting any more bytes (unloaded), and the FIFO filled up. Buffer A was the next buffer to load, and when it drained the FIFO the overrun error was passed up to the DMA and flagged with this bit.
  • Page 110 EM358x SCx_TXBEGA SC1_TXBEGA Transmit DMA Begin Address Register A Address: 0x4000C810 Reset: 0x20000000 SC2_TXBEGA Transmit DMA Begin Address Register A Address: 0x4000C010 Reset: 0x20000000 SC_TXBEGA SC_TXBEGA Bitname Bitfield Access Description SC_TXBEGA [15:0] DMA transmit buffer A start address. Rev. 0.4...
  • Page 111 EM358x SCx_TXBEGB SC1_TXBEGB Transmit DMA Begin Address Register B Address: 0x4000C818 Reset: 0x20000000 SC2_TXBEGB Transmit DMA Begin Address Register B Address: 0x4000C018 Reset: 0x20000000 SC_TXBEGB SC_TXBEGB Bitname Bitfield Access Description SC_TXBEGB [15:0] DMA transmit buffer B start address. Rev. 0.4...
  • Page 112 EM358x SCx_TXENDA SC1_TXENDA Transmit DMA End Address Register A Address: 0x4000C814 Reset: 0x20000000 SC2_TXENDA Transmit DMA End Address Register A Address: 0x4000C014 Reset: 0x20000000 SC_TXENDA SC_TXENDA Bitname Bitfield Access Description SC_TXENDA [15:0] Address of the last byte that will be read from the DMA transmit buffer A. Rev.
  • Page 113 EM358x SCx_TXENDB SC1_TXENDB Transmit DMA End Address Register B Address: 0x4000C81C Reset: 0x20000000 SC2_TXENDB Transmit DMA End Address Register B Address: 0x4000C01C Reset: 0x20000000 SC_TXENDB SC_TXENDB Bitname Bitfield Access Description SC_TXENDB [15:0] Address of the last byte that will be read from the DMA transmit buffer B. Rev.
  • Page 114 EM358x SCx_TXCNT SC1_TXCNT Transmit DMA Count Register Address: 0x4000C828 Reset: 0x0 SC2_TXCNT Transmit DMA Count Register Address: 0x4000C028 Reset: 0x0 SC_TXCNT SC_TXCNT Bitname Bitfield Access Description SC_TXCNT [15:0] The offset from the start of the active DMA transmit buffer from which the next byte will be read.
  • Page 115 EM358x SCx_RXBEGA SC1_RXBEGA Receive DMA Begin Address Register A Address: 0x4000C800 Reset: 0x20000000 SC2_RXBEGA Receive DMA Begin Address Register A Address: 0x4000C000 Reset: 0x20000000 SC_RXBEGA SC_RXBEGA Bitname Bitfield Access Description SC_RXBEGA [15:0] DMA receive buffer A start address. Rev. 0.4...
  • Page 116 EM358x SCx_RXBEGB SC1_RXBEGB Receive DMA Begin Address Register B Address: 0x4000C808 Reset: 0x20000000 SC2_RXBEGB Receive DMA Begin Address Register B Address: 0x4000C008 Reset: 0x20000000 SC_RXBEGB SC_RXBEGB Bitname Bitfield Access Description SC_RXBEGB [15:0] DMA receive buffer B start address. Rev. 0.4...
  • Page 117 EM358x SCx_RXENDA SC1_RXENDA Receive DMA End Address Register A Address: 0x4000C804 Reset: 0x20000000 SC2_RXENDA Receive DMA End Address Register A Address: 0x4000C004 Reset: 0x20000000 SC_RXENDA SC_RXENDA Bitname Bitfield Access Description SC_RXENDA [15:0] Address of the last byte that will be written in the DMA receive buffer A. Rev.
  • Page 118 EM358x SCx_RXENDB SC1_RXENDB Receive DMA End Address Register B Address: 0x4000C80C Reset: 0x20000000 SC2_RXENDB Receive DMA End Address Register B Address: 0x4000C00C Reset: 0x20000000 SC_RXENDB SC_RXENDB Bitname Bitfield Access Description SC_RXENDB [15:0] Address of the last byte that will be written in the DMA receive buffer B. Rev.
  • Page 119 EM358x SCx_RXCNTA SC1_RXCNTA Receive DMA Count Register A Address: 0x4000C820 Reset: 0x0 SC2_RXCNTA Receive DMA Count Register A Address: 0x4000C020 Reset: 0x0 SC_RXCNTA SC_RXCNTA Bitname Bitfield Access Description SC_RXCNTA [15:0] The offset from the start of DMA receive buffer A at which the next byte will be written.
  • Page 120 EM358x SCx_RXCNTB SC1_RXCNTB Receive DMA Count Register B Address: 0x4000C824 Reset: 0x0 SC2_RXCNTB Receive DMA Count Register B Address: 0x4000C024 Reset: 0x0 SC_RXCNTB SC_RXCNTB Bitname Bitfield Access Description SC_RXCNTB [15:0] The offset from the start of DMA receive buffer B at which the next byte will be written.
  • Page 121 EM358x SCx_RXCNTSAVED SC1_RXCNTSAVED Saved Receive DMA Count Register Address: 0x4000C870 Reset: 0x0 SC2_RXCNTSAVED Saved Receive DMA Count Register Address: 0x4000C070 Reset: 0x0 SC_RXCNTSAVED SC_RXCNTSAVED Bitname Bitfield Access Description SC_RXCNTSAVED [15:0] Receive DMA count saved in SPI slave mode when nSSEL deasserts. The count is only saved the first time nSSEL deasserts.
  • Page 122 EM358x SCx_RXERRA SC1_RXERRA DMA First Receive Error Register A Address: 0x4000C834 Reset: 0x0 SC2_RXERRA DMA First Receive Error Register A Address: 0x4000C034 Reset: 0x0 SC_RXERRA SC_RXERRA Bitname Bitfield Access Description SC_RXERRA [15:0] The offset from the start of DMA receive buffer A of the first byte received with a parity, frame, or overflow error.
  • Page 123 EM358x SCx_RXERRB SC1_RXERRB DMA First Receive Error Register B Address: 0x4000C838 Reset: 0x0 SC2_RXERRB DMA First Receive Error Register B Address: 0x4000C038 Reset: 0x0 SC_RXERRB SC_RXERRB Bitname Bitfield Access Description SC_RXERRB [15:0] The offset from the start of DMA receive buffer B of the first byte received with a parity, frame, or overflow error.

  • Page 124: Usb Device

    EM358x 9 USB Device 9.1 Overview The EM3582, EM3586, and EM3588 have a USB 2.0-compliant full-speed (12 Mbps) device peripheral, with on- chip transceiver. Other EM358x variants (EM3581, EM3585, and EM3587) do not support USB. The EM358x only supports one configuration (configuration 0) and two interfaces. By default all logical endpoints are on the first interface (interface 0), while the USB_INTF1SEL register enables associating logical endpoints with interface 1.

  • Page 125: Gpio Usage And Usb Pin Assignments

    EM358x 9.5 GPIO Usage and USB Pin Assignments Three GPIO are required for all USB design. A fourth GPIO is required when the system is a self powered device. The USB interface is available as an alternate function on 2 GPIO pins: PA0 and PA1. USBDM is on PA0, and USBDP is on PA1.

  • Page 126: Endpoints

    EM358x Figure 9-2. EM358x USB Application Circuit – Self Powered Device 9.7 Endpoints EM358x supports up to six endpoints (in addition to the control endpoint 0). The USB peripheral is interfaced to the CPU through memory mapped registers for control, and DMA for data. Before the device will respond to the USB bus, it must be configured to define its endpoint status and enable the device.

  • Page 127: Buffers And Dma

    EM358x Table 9-1. Endpoints Endpoint Number Max Packet Size in Bytes Type Direction Buffer Offset Endpoint 0 Control 0x000 0x008 Endpoint 1 Bulk or Interrupt 0x010 0x018 Endpoint 2 Bulk or Interrupt 0x020 0x028 Endpoint 3 Bulk or Interrupt 0x030 0x070 Endpoint 4 Bulk or Interrupt...
  • Page 128 EM358x Table 9-2. Software Handled Standard Commands Command Target Data? Comments Get Descriptor Device Get the device descriptor. Set Descriptor Device Set the device descriptor. Get Descriptor Configuration Get the configuration descriptor. Set Descriptor Configuration Set the configuration descriptor. Synch Frame Endpoint Synchronize frames in an endpoint.

  • Page 129: Set Up And Configuration

    EM358x 9.10 Set Up and Configuration It is best to have the enumeration pull-up resistor configured for the disconnected state whenever modifying the USB configuration so that the host does not attempt enumeration before the USB core and the USB software on the device is fully configured and ready to interact with the host.

  • Page 130: Dma Usage And Transfers

    EM358x enumeration process. The GPIO and interrupt configuration used follows the same procedure described for External Interrupts.  Configure the GPIO as a simple input.  Disable interrupt triggering by clearing to 0 the IRQ register being used for the GPIO. This will be one of the registers GPIO_INTCFGA, GPIO_INTCFGB, GPIO_INTCFGC, or GPIO_INTCFGD.

  • Page 131: Suspend And Resume

    EM358x 9.12 Suspend and Resume The USB specification details the maximum allowable current draw while suspended and how quickly a device must achieve this current draw. Fully supporting all of electrical compliance for the purpose of an EM358x device passing USB Certification is tightly coupled with the application being run on the EM358x and the larger EM358x system.

  • Page 132: Registers

    EM358x 9.14 Registers x = EP number. y = buffer A or B USB_CTRL USB Control Register Address: 0x4001105C Reset: 0x4 USB_RESET USB_ENBUFOU USB_ENBUFOU USB_ENBUFOU USB_ENBUFOU USB_ENBUFOUT USB_ENBUFOU USB_ENBUFOU CTRL TEP6B TEP5B TEP4B TEP3B EP2B TEP1B TEP0B USB_ENBUFINE USB_ENBUFINE USB_ENBUFINE USB_ENBUFINE USB_ENBUFINE USB_ENBUFINE...
  • Page 133 EM358x USB_CLRFEP0STALL Set this bit for the USB core to send STALL on ClearFeature (EPO), else send ACK. EP0 must always process the control commands so the USB core will not actually respond with STALL to subsequent control commands. Instead this bit is a means of indicating to the host that ClearFeature(EP0) is acknowledged or unexpected.
  • Page 134 EM358x USB_STATUS USB Status Register Address: 0x4001106C Reset: 0x0 USB_RESETSTAT USB_SUSPENDED USB_TIMESTAMP USB_TIMESTAMP Bitname Bitfield Access Description USB_RESETSTAT [12] This bit is set while USB reset is active. The rising edge of the reset status generates the INT_USBRESET interrupt. USB_SUSPENDED [11] This bit is set while the device is suspended.
  • Page 135 EM358x USB_ENABLEIN USB Endpoint IN Enables Register Address: 0x4001104C Reset: 0x1 USB_ENABLEIN USB_ENABLEIN USB_ENABLEIN USB_ENABLEIN USB_ENABLEINEP USB_ENABLEINEP USB_ENABLEINEP Bitname Bitfield Access Description USB_ENABLEINEP6 Set this bit to enable endpoint 6 buffer A IN. USB_ENABLEINEP5 Set this bit to enable endpoint 5 buffer A IN. USB_ENABLEINEP4 Set this bit to enable endpoint 4 buffer A IN.
  • Page 136 EM358x USB_ENABLEOUT USB Endpoint OUT Enables Register Address: 0x40011050 Reset: 0x1 0 USB_ENABLEOU USB_ENABLEOU USB_ENABLEOU USB_ENABLEOU USB_ENABLEOU USB_ENABLEOU USB_ENABLEOU TEP6 TEP5 TEP4 TEP3 TEP2 TEP1 TEP0 Bitname Bitfield Access Description USB_ENABLEOUTEP6 Set this bit to enable endpoint 6 buffer A OUT. USB_ENABLEOUTEP5 Set this bit to enable endpoint 5 buffer A OUT.
  • Page 137 EM358x USB_INTF1SEL USB Endpoint Interface 1 Select Register Address: 0x40011074 Reset: 0x0 USB_INTF1SELEN USB_INTF1SELE USB_INTF1SELE USB_INTF1SELE USB_INTF1SELE USB_INTF1SELE USB_INTF1SELE Bitname Bitfield Access Description USB_INTF1SELEN [31] Set this bit to enable endpoints to be associated with Interface 1. Clear this bit to keep endpoints only associated with Interface 0.
  • Page 138 EM358x USB_BUFBASEy USB_BUFBASEA Base Address of Endpoint A Buffers in Main Memory Register Address: 0x40011000 Reset: 0x20000000 USB_BUFBASEB Base Address of Endpoint B Buffers in Main Memory Register Address: 0x40011004 Reset: 0x20000000 USB_BUFBASEy_FIELD USB_BUFBASEy_FIELD USB_BUFBASEy_FIELD USB_BUFBASEy_FIELD Bitname Bitfield Access Description Write this register with a RAM address to position buffer y in RAM.
  • Page 139 EM358x USB_TXLOAD USB TX Buffer A and B Load Register Address: 0x40011008 Reset: 0x0 USB_TXLOADEP USB_TXLOADEP USB_TXLOADEP USB_TXLOADEP USB_TXLOADEP USB_TXLOADEP USB_TXLOADE USB_TXLOADEP USB_TXLOADEP USB_TXLOADEP USB_TXLOADEP USB_TXLOADEP USB_TXLOADEP USB_TXLOADE Bitname Bitfield Access Description USB_TXLOADEP6B [14] Write this bit to load endpoint 6, buffer B for transmit. Auto-clears to 0. USB_TXLOADEP5B [13] Write this bit to load endpoint 5, buffer B for transmit.
  • Page 140 EM358x USB_TXACTIVE USB Buffer A and Buffer B Transmit Active Status Register Address: 0x4001100C Reset: 0x0 0 USB_TXACTIVEE USB_TXACTIVEE USB_TXACTIVEE USB_TXACTIVEE USB_TXACTIVEE USB_TXACTIVEE USB_TXACTIVEE 0 USB_TXACTIVEE USB_TXACTIVEE USB_TXACTIVEE USB_TXACTIVEE USB_TXACTIVEE USB_TXACTIVEE USB_TXACTIVEE Bitname Bitfield Access Description USB_TXACTIVEEP6B [14] This bit is set while endpoint 6, buffer B is active. USB_TXACTIVEEP5B [13] This bit is set while endpoint 5, buffer B is active.
  • Page 141 EM358x USB_TXBUFSIZEEP0y USB_TXBUFSIZEEP0A Number of Bytes to Transmit for Endpoint 0, Buffer A Register Address: 0x40011010 Reset: 0x0 USB_TXBUFSIZEEP0B Number of Bytes to Transmit for Endpoint 0, Buffer B Register Address: 0x4001102C Reset: 0x0 USB_TXBUFSIZEEP0y Bitname Bitfield Access Description USB_TXBUFSIZEEP0y [3:0] Size, in bytes, of data to transmit for endpoint 0, buffer y.
  • Page 142 EM358x USB_TXBUFSIZEEP1y USB_TXBUFSIZEEP1A Number of Bytes to Transmit for Endpoint 1, Buffer A Register Address: 0x40011014 Reset: 0x0 USB_TXBUFSIZEEP1B Number of Bytes to Transmit for Endpoint 1, Buffer B Register Address: 0x40011030 Reset: 0x0 USB_TXBUFSIZEEP1y Bitname Bitfield Access Description USB_TXBUFSIZEEP1y [3:0] Size, in bytes, of data to transmit for endpoint 1, buffer y.
  • Page 143 EM358x USB_TXBUFSIZEEP2y USB_TXBUFSIZEEP2A Number of Bytes to Transmit for Endpoint 2, Buffer A Register Address: 0x40011018 Reset: 0x0 USB_TXBUFSIZEEP2B Number of Bytes to Transmit for Endpoint 2, Buffer B Register Address: 0x40011034 Reset: 0x0 USB_TXBUFSIZEEP2y Bitname Bitfield Access Description USB_TXBUFSIZEEP2y [3:0] Size, in bytes, of data to transmit for endpoint 2, buffer y.
  • Page 144 EM358x USB_TXBUFSIZEEP3y USB_TXBUFSIZEEP3A Number of Bytes to Transmit for Endpoint 3, Buffer A Register Address: 0x4001101C Reset: 0x0 USB_TXBUFSIZEEP3B Number of Bytes to Transmit for Endpoint 3, Buffer B Register Address: 0x40011038 Reset: 0x0 USB_TXBUFSIZEEP3y Bitname Bitfield Access Description USB_TXBUFSIZEEP3y [6:0] Size, in bytes, of data to transmit for endpoint 3, buffer y.
  • Page 145 EM358x USB_TXBUFSIZEEP4y USB_TXBUFSIZEEP4A Number of Bytes to Transmit for Endpoint 4, Buffer A Register Address: 0x40011020 Reset: 0x0 USB_TXBUFSIZEEP4B Number of Bytes to Transmit for Endpoint 4, Buffer B Register Address: 0x4001103C Reset: 0x0 USB_TXBUFSIZEEP4y Bitname Bitfield Access Description USB_TXBUFSIZEEP4y [5:0] Size, in bytes, of data to transmit for endpoint 4, buffer y.
  • Page 146 EM358x USB_TXBUFSIZEEP5y USB_TXBUFSIZEEP5A Number of Bytes to Transmit for Endpoint 5, Buffer A Register Address: 0x40011024 Reset: 0x0 USB_TXBUFSIZEEP5B Number of Bytes to Transmit for Endpoint 5, Buffer B Register Address: 0x40011040 Reset: 0x0 USB_TXBUFSIZEEP5y Bitname Bitfield Access Description USB_TXBUFSIZEEP5y [6:0] Size, in bytes, of data to transmit for endpoint 5, buffer y.
  • Page 147 EM358x USB_TXBUFSIZEEP6y USB_TXBUFSIZEEP6A Number of Bytes to Transmit for Endpoint 6, Buffer A Register Address: 0x40011028 Reset: 0x0 USB_TXBUFSIZEEP6B Number of Bytes to Transmit for Endpoint 6, Buffer B Register Address: 0x40011044 Reset: 0x0 USB_TXBUFSIZEEP6y USB_TXBUFSIZEEP6y Bitname Bitfield Access Description USB_TXBUFSIZEEP6y [9:0] Size, in bytes, of data to transmit for endpoint 6, buffer y.
  • Page 148 EM358x USB_RXVALID USB Buffer A and Buffer B Reception Valid Status Register Address: 0x40011048 Reset: 0x0 0 USB_RXVALIDEP USB_RXVALIDEP USB_RXVALIDEP USB_RXVALIDEP USB_RXVALIDEP USB_RXVALIDEP USB_RXVALIDEP 0 USB_RXVALIDEP USB_RXVALIDEP USB_RXVALIDEP USB_RXVALIDEP USB_RXVALIDEP USB_RXVALIDEP USB_RXVALIDEP Bitname Bitfield Access Description USB_RXVALIDEP6B [14] This bit is set when endpoint 6, buffer B reception is valid. USB_RXVALIDEP5B [13] This bit is set when endpoint 5, buffer B reception is valid.
  • Page 149 EM358x USB_RXBUFSIZEEP0y USB_RXBUFSIZEEP0A Number of Bytes Received in Endpoint 0, Buffer A Register Address: 0x40011078 Reset: 0x0 USB_RXBUFSIZEEP0B Number of Bytes Received in Endpoint 0, Buffer B Register Address: 0x40011094 Reset: 0x0 USB_RXBUFSIZEEP0y Bitname Bitfield Access Description USB_RXBUFSIZEEP0y [3:0] Size, in bytes, of data received on endpoint 0, buffer y. This register is valid only after the corresponding USB_RXVALIDEP0y bit is set.
  • Page 150 EM358x USB_RXBUFSIZEEP1y USB_RXBUFSIZEEP1A Number of Bytes Received in Endpoint 1, Buffer A Register Address: 0x4001107C Reset: 0x0 USB_RXBUFSIZEEP1B Number of Bytes Received in Endpoint 1, Buffer B Register Address: 0x40011098 Reset: 0x0 USB_RXBUFSIZEEP1y Bitname Bitfield Access Description USB_RXBUFSIZEEP1y [3:0] Size, in bytes, of data received on endpoint 1, buffer y. This register is valid only after the corresponding USB_RXVALIDEP1y bit is set.
  • Page 151 EM358x USB_RXBUFSIZEEP2y USB_RXBUFSIZEEP2A Number of Bytes Received in Endpoint 2, Buffer A Register Address: 0x40011080 Reset: 0x0 USB_RXBUFSIZEEP2B Number of Bytes Received in Endpoint 2, Buffer B Register Address: 0x4001109C Reset: 0x0 USB_RXBUFSIZEEP2y Bitname Bitfield Access Description USB_RXBUFSIZEEP2y [3:0] Size, in bytes, of data received on endpoint 2, buffer y. This register is valid only after the corresponding USB_RXVALIDEP2y bit is set.
  • Page 152 EM358x USB_RXBUFSIZEEP3y USB_RXBUFSIZEEP3A Number of Bytes Received in Endpoint 3, Buffer A Register Address: 0x40011084 Reset: 0x0 USB_RXBUFSIZEEP3B Number of Bytes Received in Endpoint 3, Buffer B Register Address: 0x400110A0 Reset: 0x0 USB_RXBUFSIZEEP3y Bitname Bitfield Access Description USB_RXBUFSIZEEP3y [6:0] Size, in bytes, of data received on endpoint 3, buffer y. This register is valid only after the corresponding USB_RXVALIDEP3y bit is set.
  • Page 153 EM358x USB_RXBUFSIZEEP4y USB_RXBUFSIZEEP4A Number of Bytes Received in Endpoint 4, Buffer A Register Address: 0x40011088 Reset: 0x0 USB_RXBUFSIZEEP4B Number of Bytes Received in Endpoint 4, Buffer B Register Address: 0x400110A4 Reset: 0x0 USB_RXBUFSIZEEP4y Bitname Bitfield Access Description USB_RXBUFSIZEEP4y [5:0] Size, in bytes, of data received on endpoint 4, buffer y. This register is valid only after the corresponding USB_RXVALIDEP4y bit is set.
  • Page 154 EM358x USB_RXBUFSIZEEP5y USB_RXBUFSIZEEP5A Number of Bytes Received in Endpoint 5, Buffer A Register Address: 0x4001108C Reset: 0x0 USB_RXBUFSIZEEP5B Number of Bytes Received in Endpoint 5, Buffer B Register Address: 0x400110A8 Reset: 0x0 USB_RXBUFSIZEEP5y Bitname Bitfield Access Description USB_RXBUFSIZEEP5y [6:0] Size, in bytes, of data received on endpoint 5, buffer y. This register is valid only after the corresponding USB_RXVALIDEP5y bit is set.
  • Page 155 EM358x USB_RXBUFSIZEEP6y USB_RXBUFSIZEEP6A Number of Bytes Received in Endpoint 6, Buffer A Register Address: 0x40011090 Reset: 0x0 USB_RXBUFSIZEEP6B Number of Bytes Received in Endpoint 6, Buffer B Register Address: 0x400110AC Reset: 0x0 USB_RXBUFSIZEEP6y USB_RXBUFSIZEEP6y Bitname Bitfield Access Description USB_RXBUFSIZEEP6y [9:0] Size, in bytes, of data received on endpoint 6, buffer y.
  • Page 156 EM358x USB_BUFCLR USB IN Buffer Clear Register Address: 0x40011064 Reset: 0x0 USB_BUFCLRIN USB_BUFCLRIN USB_BUFCLRIN USB_BUFCLRIN USB_BUFCLRIN USB_BUFCLRIN USB_BUFCLRIN Bitname Bitfield Access Description USB_BUFCLRINEP6 Write this bit to force clearing of endpoint 6 IN buffer. Auto-clears to 0. USB_BUFCLRINEP5 Write this bit to force clearing of endpoint 5 IN buffer. Auto-clears to 0. USB_BUFCLRINEP4 Write this bit to force clearing of endpoint 4 IN buffer.
  • Page 157 EM358x USB_STALLIN USB Endpoint IN Stall Register Address: 0x40011054 Reset: 0x0 USB_STALLINEP USB_STALLINEP USB_STALLINEP USB_STALLINEP USB_STALLINEP USB_STALLINEP USB_STALLINEP Bitname Bitfield Access Description USB_STALLINEP6 Write this bit to stall endpoint 6 IN. This bit will not auto-clear. USB_STALLINEP5 Write this bit to stall endpoint 5 IN. This bit will not auto-clear. USB_STALLINEP4 Write this bit to stall endpoint 4 IN.
  • Page 158 EM358x USB_STALLOUT USB Endpoint OUT Stall Register Address: 0x40011054 Reset: 0x0 USB_STALLOUT USB_STALLOUT USB_STALLOUT USB_STALLOUT USB_STALLOUT USB_STALLOUT USB_STALLOUT Bitname Bitfield Access Description USB_STALLOUTEP6 Write this bit to stall endpoint 6 OUT. This bit will not auto-clear. USB_STALLOUTEP5 Write this bit to stall endpoint 5 OUT. This bit will not auto-clear. USB_STALLOUTEP4 Write this bit to stall endpoint 4 OUT.
  • Page 159 EM358x USB_RESUME USB Resume Register Address: 0x40011068 Reset: 0x0 USB_RESUME Bitname Bitfield Access Description USB_RESUME Write this bit to resume from the suspended state. This activity is also known as remote-wakeup. Auto-clears to 0. Rev. 0.4...
  • Page 160 EM358x USB_PIPECLR USB Force DMA Pipeline Clearing Register Address: 0x40011060 Reset: 0x0 USB_RXPIPECLR USB_TXPIPECLR Bitname Bitfield Access Description USB_RXPIPECLR Write this bit to force clearing of the receive DMA pipeline. Auto-clears to 0. USB_TXPIPECLR Write this bit to force clearing of the transmit DMA pipeline. Auto-clears to 0. Rev.
  • Page 161 EM358x INT_USBFLAG USB Interrupt Flag Register Address: 0x4000A888 Reset: 0x0 INT_USBWAKE INT_USBRESU INT_USBSUSP INT_USBRESET INT_USBSOF INT_USBNAK INT_USBPIPER INT_USBPIPET XOVF XUND INT_USBBUFR INT_USBBUFTX INT_USBRXVAL INT_USBRXVAL INT_USBRXVAL INT_USBRXVAL INT_USBRXVAL INT_USBRXVAL XOVF IDEP6 IDEP5 IDEP4 IDEP3 IDEP3 IDEP1 INT_USBRXVA INT_USBTXACT INT_USBTXACT INT_USBTXACT INT_USBTXACT INT_USBTXACT INT_USBTXACT INT_USBTXACT...
  • Page 162 EM358x Bitname Bitfield Access Description INT_USBWAKEUP [23] A successful remote wakeup by this device pends this interrupt. INT_USBRESUME [22] When suspended, a resume on the bus pends this interrupt. INT_USBSUSPEND [21] Suspending this device pends this interrupt. INT_USBRESET [20] When a USB reset occurs it resets the core and pends this interrupt. INT_USBSOF [19] A start of frame packet pends this interrupt.
  • Page 163 EM358x INT_USBCFG USB Interrupt Configuration Register Address: 0x4000A88C Reset: 0x0 INT_USBWAKE INT_USBRESU INT_USBSUSP INT_USBRESET INT_USBSOF INT_USBNAK INT_USBPIPER INT_USBPIPET XOVF XUND INT_USBBUFR INT_USBBUFTX INT_USBRXVAL INT_USBRXVAL INT_USBRXVAL INT_USBRXVAL INT_USBRXVAL INT_USBRXVAL XOVF IDEP6 IDEP5 IDEP4 IDEP3 IDEP3 IDEP1 INT_USBRXVA INT_USBTXACT INT_USBTXACT INT_USBTXACT INT_USBTXACT INT_USBTXACT INT_USBTXACT INT_USBTXACT...
  • Page 164 EM358x Bitname Bitfield Access Description INT_USBWAKEUP [23] A successful remote wakeup by this device interrupt enable. INT_USBRESUME [22] When suspended, a resume on the bus interrupt enable. INT_USBSUSPEND [21] Suspending this device interrupt enable. INT_USBRESET [20] When a USB reset occurs it resets the core interrupt enable. INT_USBSOF [19] A start of frame packet interrupt enable.

  • Page 165: General Purpose Timers (Tim1 And Tim2)

    EM358x 10 General Purpose Timers (TIM1 and TIM2) 10.1 Introduction Each of the EM358x’s two general-purpose timers consists of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM).

  • Page 166: Gpio Usage

    EM358x Figure 10-1. General-Purpose Timer Block Diagram The internal signals shown in Figure 10-1 are described in the Timer Signal Descriptions section, and are Note: used throughout the text to describe how the timer components are interconnected. 10.2 GPIO Usage The timers can optionally use GPIOs in the PA and PB ports for external inputs or outputs.

  • Page 167: Timer Functional Description

    EM358x Many of the GPIOs that can be assigned as timer outputs can also be used by another on-chip peripheral such as a serial controller. Using a GPIO as a timer output takes precedence over another peripheral function, as long as the channel is configured as an output in the TIMx_CCMR1 register and is enabled in the TIMx_CCER register.

  • Page 168: Counter Modes

    EM358x 10.3.1.1 Prescaler The prescaler can divide the counter clock frequency by power of two from 1 through 32768. It is based on a 16- bit counter controlled through the 4-bit TIM_PSCEXP bit field in the TIMx_PSC register. The factor by which the TIM_PSCEXP counter is divided is two raised to the power TIM_PSCEXP (2 It can be changed on the fly as this control register is buffered.
  • Page 169 EM358x Figure 10-3, Figure 10-4, Figure 10-5, and Figure 10-6 show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36. Figure 10-3. Counter Timing Diagram, Internal Clock Divided by 1 Figure 10-4. Counter Timing Diagram, Internal Clock Divided by 4 Figure 10-5.
  • Page 170 EM358x Figure 10-6. Counter Timing Diagram, Update Event when TIM_ARBE = 1 (TIMx_ARR buffered) 10.3.2.2 Down-Counting Mode In down-counting mode, the counter counts from the auto-reload value (contents of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. A UEV can be generated at each counter underflow, by setting the TIM_UG bit in the TIMx_EGR register, or by using the slave mode controller.
  • Page 171 EM358x Figure 10-8. Counter Timing Diagram, Internal Clock Divided by 4 10.3.2.3 Center-Aligned Mode (Up/Down Counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register) – 1 and generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event.
  • Page 172 EM358x Figure 10-9. Counter Timing Diagram, Internal Clock Divided by 1, TIMx_ARR = 0x6 Figure 10-10. Counter Timing Diagram, Update Event with TIM_ARBE = 1 (counter underflow) Rev. 0.4...

  • Page 173: Clock Selection

    EM358x Figure 10-11. Counter Timing Diagram, Update Event with TIM_ARBE = 1 (counter overflow) 10.3.3 Clock Selection The counter clock can be provided by the following clock sources:  Internal clock (PCLK)  External clock mode 1: external input pin (TIy) ...
  • Page 174 EM358x 10.3.3.2 External Clock Source Mode 1 This mode is selected when TIM_SMS = 111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 10-13 shows the registers and signals used in the example that follows. Figure 10-13.
  • Page 175 EM358x Table 10-2. TIM_EXTRIGSEL Clock Signal Selection TIM_EXTRIGSEL bits Clock Signal Selection PCLK (peripheral clock). When running from the 24 MHz crystal oscillator, the PCLK frequency is 12 MHz. When the 12 MHz RC oscillator is in use, the frequency is 6 MHz. Calibrated 1 kHz internal RC oscillator Optional 32.786 kHz clock TIMxCLK pin.

  • Page 176: Capture/Compare Channels

    EM358x 10.3.4 Capture/Compare Channels Each capture/compare channel is built around a capture/compare register including a shadow register, an input stage for capture with digital filter, multiplexing and prescaler, and an output stage with comparator and output control. Figure 10-17 gives an overview of the input stage of one capture/compare channel. The input stage samples the corresponding TIy input to generate a filtered signal (TIyF).

  • Page 177: Input Capture Mode

    EM358x Figure 10-19 show details of the output stage of a capture/compare channel. Figure 10-19. Output Stage of Capture/Compare Channel (Channel 1) The capture/compare block is made of a buffer register and a shadow register. Writes and reads always access the buffer register.

  • Page 178: Pwm Input Mode

    EM358x To detect missed captures reliably, read captured data in TIMxCCRy before checking the missed capture/compare flag. This sequence avoids missing a capture that could happen after reading the flag and before reading the data. Software can generate IC interrupt requests by setting the corresponding TIM_CCyG bit in the TIMx_EGR Note: register.

  • Page 179: Output Compare Mode

    EM358x To force an output compare signal (OCyREF/OCy) to its active level, write 101 in the TIM_OCyM bits in the corresponding TIMx_CCMR1 register. OCyREF is forced high (OCyREF is always active high) and OCy gets the opposite value to the TIM_CCyP polarity bit. For example, TIM_CCyP = 0 defines OCy as active high, so when OCyREF is active, OCy is also set to a high level.

  • Page 180: Pwm Mode

    EM358x To control the output waveform, software can update the TIMx_CCRy register at any time, provided that the buffer register is not enabled (TIM_OCyBE = 0). Otherwise TIMx_CCRy shadow register is updated only at the next UEV. An example is given in Figure 10-21. Figure 10-21.
  • Page 181 EM358x auto-reload value in TIMx_ARR, then OCyREF is held at 1. If the compare value is 0, then OCyREF is held at 0. Figure 10-22 shows some edge-aligned PWM waveforms in an example, where TIMx_ARR = 8. Figure 10-22. Edge-Aligned PWM Waveforms (ARR = 8) 10.3.9.2 PWM Edge-Aligned Mode: Down-Counting Configuration Down-counting is active when the TIM_DIR bit in the TIMx_CR1 register is high.

  • Page 182: One-Pulse Mode

    EM358x Figure 10-23. Center-Aligned PWM Waveforms (ARR = 8) Hints on using center-aligned mode:  When starting in center-aligned mode, the current up-down configuration is used. This means that the counter counts up or down depending on the value written in the TIM_DIR bit in the TIMx_CR1 register. The TIM_DIR and TIM_CMS bits must not be changed at the same time by the software.
  • Page 183 EM358x Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. Select OPM by setting the TIM_OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value.
  • Page 184 EM358x 10.3.10.1 A Special Case: OCy Fast Enable In one-pulse mode, the edge detection on the TIy input sets the TIM_CEN bit, which enables the counter. Then the comparison between the counter and the compare value toggles the output. However, several clock cycles are needed for this operation, and it limits the minimum delay (t min) achievable.

  • Page 185: Timer Input Xor Function

    EM358x Figure 10-25 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated for when both inputs are used for counting. This might occur if the sensor is positioned near one of the switching points. This example assumes the following configuration: ...

  • Page 186: Timers And External Trigger Synchronization

    EM358x The XOR output can be used with all the timer input functions such as trigger or input capture. It is especially useful to interface to Hall effect sensors. 10.3.13 Timers and External Trigger Synchronization The timers can be synchronized with an external trigger in several modes: reset mode, gated mode, and trigger mode.
  • Page 187 EM358x The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The INT_TIMTIF flag in the INT_TIMxFLAG register is set when the counter starts and when it stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on the TI1 input.

  • Page 188: Timer Synchronization

    EM358x In the following example, shown in Figure 10-30, the up-counter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs:  Configure the external trigger input circuit: Program the TIMx_SMCR register as follows: ...
  • Page 189 EM358x Figure 10-31. Master/Slave Timer Example 10.3.15.2 Using One Timer to Enable the Other Timer In this example, shown in Figure 10-32, the enable of Timer 2 is controlled with the output compare 1 of Timer 1. Timer 2 counts on the divided internal clock only when OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (f /3).
  • Page 190 EM358x  Configure Timer 2 in gated mode: Write TIM_SMS = 101 in the TIM2_SMCR register.  Reset Timer 1: Write 1 in the TIM_UG bit (TIM1_EGR register.  Reset Timer 2 by writing 1 in the TIM_UG bit (TIM2_EGR register). ...
  • Page 191 EM358x Figure 10-34. Triggering Timer 2 with Update of Timer 1 As in the previous example, both counters can be initialized before starting counting. Figure 10-35 shows the behavior with the same configuration shown in Figure 10-34, but in trigger mode instead of gated mode (TIM_SMS = 110 in the TIM2_SMCR register).

  • Page 192: Timer Signal Descriptions

    EM358x In this example both timers are initialized before starting by setting their respective TIM_UG bits. Both Note: counters starts from 0, but an offset can be inserted between them by writing any of the counter registers (TIMx_CNT). The master/slave mode inserts a delay between CNT_EN and CK_PSC on Timer 1. Figure 10-36.

  • Page 193: Interrupts

    EM358x 10.4 Interrupts Each timer has its own top-level NVIC interrupt. Writing 1 to the INT_TIMx bit in the INT_CFGSET register enables the TIMx interrupt, and writing 1 to the INT_TIMx bit in the INT_CFGCLR register disables it. Chapter 3, Interrupt System, describes the interrupt system in detail.

  • Page 194: Registers

    EM358x 10.5 Registers TIMx_CR1 TIM1_CR1 Timer 1 Control Register 1 Address: 0x4000F000 Reset: 0x0 TIM2_CR1 Timer 2 Control Register 1 Address: 0x40010000 Reset: 0x0 TIM_ARBE TIM_CMS TIM_DIR TIM_OPM TIM_URS TIM_UDIS TIM_CEN Bitname Bitfield Access Description TIM_ARBE Auto-Reload Buffer Enable. 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered.
  • Page 195 EM358x Bitname Bitfield Access Description TIM_OPM One Pulse Mode. 0: Counter does not stop counting at the next UEV. 1: Counter stops counting at the next UEV (and clears the bit TIM_CEN). TIM_URS Update Request Source. 0: When enabled, update interrupt requests are sent as soon as registers are updated (counter overflow/underflow, setting the TIM_UG bit, or update generation through the slave mode controller).
  • Page 196 EM358x TIMx_CR2 TIM1_CR2 Timer 1 Control Register 2 Address: 0x4000F004 Reset: 0x0 TIM2_CR2 Timer 2 Control Register 2 Address: 0x40010004 Reset: 0x0 TIM_TI1S TIM_MMS Bitname Bitfield Access Description TIM_TI1S TI1 Selection. 0: TI1M (input of the digital filter) is connected to TI1 input. 1: TI1M is connected to the TI_HALL inputs (XOR combination).
  • Page 197 EM358x TIMx_SMCR TIM1_SMCR Timer 1 Slave Mode Control Register Address: 0x4000F008 Reset: 0x0 TIM2_SMCR Timer 2 Slave Mode Control Register Address: 0x40010008 Reset: 0x0 TIM_ETP TIM_ECE TIM_ETPS TIM_ETF TIM_MSM TIM_TS TIM_SMS Bitname Bitfield Access Description TIM_ETP [15] External Trigger Polarity. This bit selects whether ETR or the inverse of ETR is used for trigger operations.
  • Page 198 EM358x Bitname Bitfield Access Description TIM_ETF [11:8] External Trigger Filter. This defines the frequency used to sample the ETRP signal, Fsampling, and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: Fsampling=PCLK, no filtering.
  • Page 199 EM358x Bitname Bitfield Access Description TIM_SMS [2:0] Slave Mode Selection. When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. If TIM_CEN = 1 then the prescaler is clocked directly by the internal clock. 001: Encoder mode 1.
  • Page 200 EM358x TIMx_EGR TIM1_EGR Timer 1 Event Generation Register Address: 0x4000F014 Reset: 0x0 TIM2_EGR Timer 2 Event Generation Register Address: 0x40010014 Reset: 0x0 TIM_TG TIM_CC4G TIM_CC3G TIM_CC2G TIM_CC1G TIM_UG Bitname Bitfield Access Description TIM_TG Trigger Generation. 0: Does nothing. 1: Sets the TIM_TIF flag in the INT_TIMxFLAG register. TIM_CC4G Capture/Compare 4 Generation.
  • Page 201 EM358x Bitname Bitfield Access Description TIM_CC1G Capture/Compare 1 Generation. 0: Does nothing. 1: If CC1 configured as output channel: The TIM_CC1IF flag is set. If CC1 configured as input channel: The TIM_CC1IF flag is set. The INT_TIMMISSCC1IF flag is set if the TIM_CC1IF flag was already high.
  • Page 202 EM358x TIMx_CCMR1 TIM1_CCMR1 Timer 1 Capture/Compare Mode Register 1 Address: 0x4000F018 Reset: 0x0 TIM2_CCMR1 Timer 2 Capture/Compare Mode Register 1 Address: 0x40010018 Reset: 0x0 TIM_OC2M TIM_OC2BE TIM_OC2FE TIM_CC2S TIM_IC2F TIM_IC2PSC TIM_OC1M TIM_OC1BE TIM_OC1FE TIM_CC1S TIM_IC1F TIM_IC1PSC Timer channels can be programmed as inputs (capture mode) or outputs (compare mode). The direction of channel y is defined by TIM_CCyS in this register.
  • Page 203 EM358x Bitname Bitfield Access Description TIM_OC2BE [11] Output Compare 2 Buffer Enable. (Applies only if TIM_CC2S = 0.) 0: Buffer register for TIMx_CCR2 is disabled. TIMx_CCR2 can be written at anytime, the new value is used by the shadow register immediately. 1: Buffer register for TIMx_CCR2 is enabled.
  • Page 204 EM358x Bitname Bitfield Access Description TIM_CC2S [9:8] Capture / Compare 2 Selection. This configures the channel as an output or an input. If an input, it selects the input source. 00: Channel is an output. 01: Channel is an input and is mapped to TI2. 10: Channel is an input and is mapped to TI1.
  • Page 205 EM358x TIMx_CCMR2 TIM1_CCMR2 Timer 1 Capture/Compare Mode Register 2 Address: 0x4000F01C Reset: 0x0 TIM2_CCMR2 Timer 2 Capture/Compare Mode Register 2 Address: 0x4001001C Reset: 0x0 TIM_OC4M TIM_OC4BE TIM_OC4FE TIM_CC4S TIM_IC4F TIM_IC4PSC TIM_OC3M TIM_OC3BE TIM_OC3FE TIM_CC3S TIM_IC3F TIM_IC3PSC Timer channels can be programmed as inputs (capture mode) or outputs (compare mode). The direction of channel y is defined by TIM_CCyS in this register.
  • Page 206 EM358x Bitname Bitfield Access Description TIM_OC4BE [11] Output Compare 4 Buffer Enable. (Applies only if TIM_CC4S = 0.) 0: Buffer register for TIMx_CCR4 is disabled. TIMx_CCR4 can be written at anytime, the new value is used by the shadow register immediately. 1: Buffer register for TIMx_CCR4 is enabled.
  • Page 207 EM358x Bitname Bitfield Access Description TIM_CC4S [9:8] Capture / Compare 4 Selection. This configures the channel as an output or an input. If an input, it selects the input source. 00: Channel is an output. 01: Channel is an input and is mapped to TI4. 10: Channel is an input and is mapped to TI3.
  • Page 208 EM358x TIMx_CCER TIM1_CCER Timer 1 Capture/Compare Enable Register Address: 0x4000F020 Reset: 0x0 TIM2_CCER Timer 2 Capture/Compare Enable Register Address: 0x40010020 Reset: 0x0 TIM_CC4P TIM_CC4E TIM_CC3P TIM_CC3E TIM_CC2P TIM_CC2E TIM_CC1P TIM_CC1E Bitname Bitfield Access Description TIM_CC4P [13] Capture/Compare 4 output Polarity. If CC4 is configured as an output channel: 0: OC4 is active high.
  • Page 209 EM358x TIMx_CNT TIM1_CNT Timer 1 Counter Register Address: 0x4000F024 Reset: 0x0 TIM2_CNT Timer 2 Counter Register Address: 0x40010024 Reset: 0x0 TIM_CNT TIM_CNT Bitname Bitfield Access Description TIM_CNT [15:0] Counter value. Rev. 0.4...
  • Page 210 EM358x TIMx_PSC TIM1_PSC Timer 1 Prescaler Register Address: 0x4000F028 Reset: 0x0 TIM2_PSC Timer 2 Prescaler Register Address: 0x40010028 Reset: 0x0 TIM_PSC Bitname Bitfield Access Description TIM_PSC [3:0] The prescaler divides the internal timer clock frequency. The counter clock frequency CK_CNT is equal to fCK_PSC / (2 ^ TIM_PSC). Clock division factors can range from 1 through 32768.
  • Page 211 EM358x TIMx_ARR TIM1_ARR Timer 1 Auto-Reload Register Address: 0x4000F02C Reset: 0xFFFF TIM2_ARR Timer 2 Auto-Reload Register Address: 0x4001002C Reset: 0xFFFF TIM_ARR TIM_ARR Bitname Bitfield Access Description TIM_ARR [15:0] TIM_ARR is the value to be loaded in the shadow auto-reload register. The auto-reload register is buffered.
  • Page 212 EM358x TIMx_CCR1 TIM1_CCR1 Timer 1 Capture/Compare Register 1 Address: 0x4000F034 Reset: 0x0 TIM2_CCR1 Timer 2 Capture/Compare Register 1 Address: 0x40010034 Reset: 0x0 TIM_CCR TIM_CCR Bitname Bitfield Access Description TIM_CCR [15:0] If the CC1 channel is configured as an output (TIM_CC1S = 0): TIM_CCR1 is the buffer value to be loaded in the actual capture/compare 1 register.
  • Page 213 EM358x TIMx_CCR2 TIM1_CCR2 Timer 1 Capture/Compare Register 2 Address: 0x4000F038 Reset: 0x0 TIM2_CCR2 Timer 2 Capture/Compare Register 2 Address: 0x40010038 Reset: 0x0 TIM_CCR TIM_CCR Bitname Bitfield Access Description TIM_CCR [15:0] See description in the TIMx_CCR1 register. Rev. 0.4...
  • Page 214 EM358x TIMx_CCR3 TIM1_CCR3 Timer 1 Capture/Compare Register 3 Address: 0x4000F03C Reset: 0x0 TIM2_CCR3 Timer 2 Capture/Compare Register 3 Address: 0x4001003C Reset: 0x0 TIM_CCR TIM_CCR Bitname Bitfield Access Description TIM_CCR [15:0] See description in the TIMx_CCR1 register. Rev. 0.4...
  • Page 215 EM358x TIMx_CCR4 TIM1_CCR4 Timer 1 Capture/Compare Register 4 Address: 0x4000F040 Reset: 0x0 TIM2_CCR4 Timer 2 Capture/Compare Register 4 Address: 0x40010040 Reset: 0x0 TIM_CCR TIM_CCR Bitname Bitfield Access Description TIM_CCR [15:0] See description in the TIMx_CCR1 register. Rev. 0.4...
  • Page 216 EM358x TIM1_OR Timer 1 Option Register Address: 0x4000F050 Reset: 0x0 TIM_ORRSVD TIM_CLKMSKEN TIM_EXTRIGSEL Bitname Bitfield Access Description TIM_ORRSVD Reserved: this bit must always be set to 0. TIM_CLKMSKEN Enables TIM1MSK when TIM1CLK is selected as the external trigger: 0 = TIM1MSK not used, 1 = TIM1CLK is ANDed with the TIM1MSK input.
  • Page 217 EM358x TIM2_OR Timer 2 Option Register Address: 0x40010050 Reset: 0x0 TIM_REMAPC4 TIM_REMAPC3 TIM_REMAPC2 TIM_REMAPC1 TIM_ORRSVD TIM_CLKMSKEN TIM_EXTRIGSEL Bitname Bitfield Access Description TIM_REMAPC4 Selects the GPIO used for TIM2C4: 0 = PA2, 1 = PB4. TIM_REMAPC3 Selects the GPIO used for TIM2C3: 0 = PA1, 1 = PB3. TIM_REMAPC2 Selects the GPIO used for TIM2C2: 0 = PA3, 1 = PB2.
  • Page 218 EM358x INT_TIMxCFG INT_TIM1CFG Timer 1 Interrupt Configuration Register Address: 0x4000A840 Reset: 0x0 INT_TIM2CFG Timer 2 Interrupt Configuration Register Address: 0x4000A844 Reset: 0x0 INT_TIMTIF INT_TIMCC4IF INT_TIMCC3IF INT_TIMCC2IF INT_TIMCC1IF INT_TIMUIF Bitname Bitfield Access Description INT_TIMTIF Trigger interrupt enable. INT_TIMCC4IF Capture or compare 4 interrupt enable. INT_TIMCC3IF Capture or compare 3 interrupt enable.
  • Page 219 EM358x INT_TIMxFLAG INT_TIM1FLAG Timer 1 Interrupt Flag Register Address: 0x4000A800 Reset: 0x0 INT_TIM2FLAG Timer 2 Interrupt Flag Register Address: 0x4000A804 Reset: 0x0 INT_TIMRSVD INT_TIMTIF INT_TIMCC4IF INT_TIMCC3IF INT_TIMCC2IF INT_TIMCC1IF INT_TIMUIF Bitname Bitfield Access Description INT_TIMRSVD [12:9] May change during normal operation. INT_TIMTIF Trigger interrupt.
  • Page 220 EM358x INT_TIMxMISS INT_TIM1MISS Timer 1 Missed Interrupt Register Address: 0x4000A818 Reset: 0x0 INT_TIM2MISS Timer 2 Missed Interrupts Register Address: 0x4000A81C Reset: 0x0 INT_TIMMISSCC4IF INT_TIMMISSCC3IF INT_TIMMISSCC2IF INT_TIMMISSCC1IF INT_TIMMISSRSVD Bitname Bitfield Access Description INT_TIMMISSCC4IF [12] Capture or compare 4 interrupt missed. INT_TIMMISSCC3IF [11] Capture or compare 3 interrupt missed.

  • Page 221: Adc (Analog To Digital Converter)

    EM358x 11 ADC (Analog to Digital Converter) The EM358x ADC is a first-order sigma-delta converter with the following features:  Resolution of up to 14 bits  Sample times as fast as 5.33 µs (188 kHz)  Differential and single-ended conversions from six external and four internal sources ...

  • Page 222: Gpio Usage

    EM358x 11.1.1 GPIO Usage A GPIO pin used by the ADC as an input or voltage reference must be configured in analog mode by writing 0 to its 4-bit field in the proper GPIO_PxCFGH/L register. Note that a GPIO pin in analog mode cannot be used for any digital functions, and GPIO_PxIN always reads it as 1.

  • Page 223: Adc Configuration Register

    EM358x To prepare the DMA channel for operation, reset it by writing the ADC_DMARST bit in the ADC_DMACFG register, then start the DMA in either linear or auto wrap mode by setting the ADC_DMALOAD bit in the ADC_DMACFG register. The ADC_DMAAUTOWRAP bit in the ADC_DMACFG register selects the DMA mode: 0 for linear mode, 1 for auto wrap mode.
  • Page 224 EM358x Table 11-3 shows the typical configurations of ADC inputs. Table 11-3. Typical ADC Input Configurations ADC P input ADC N input ADC_MUXP ADC_MUXN Purpose ADC0 VREF/2 Single-ended ADC1 VREF/2 Single-ended ADC2 VREF/2 Single-ended ADC3 VREF/2 Single-ended ADC4 VREF/2 Single-ended ADC5 VREF/2 Single-ended...

  • Page 225: Interrupts

    EM358x Table 11-4 shows the options for ADC sample times and the significant bits in the conversion results. Table 11-4. ADC Sample Times Sample Time (µs) Sample Frequency (kHz) Sample ADC_PERIOD Significant Bits Clocks 1 MHz clock 6 MHz clock 1 MHz clock 6 MHz clock 5.33...

  • Page 226: Operation

    EM358x 11.3 Operation Setting the ADC_EN bit in the ADC_CFG register enables the ADC. Once the ADC is enabled, it performs conversions continuously until it is disabled. If the ADC had previously been disabled, a 21 µs analog startup delay is automatically imposed before the ADC starts conversions. The delay timing is performed in hardware and is simply added to the time until the first conversion result is output.

  • Page 227: Adc Key Parameters

    EM358x ± 20 mV. If better absolute accuracy is required, the ADC can be configured to use an external reference. The ADC calibrates as a single-ended measurement. Differential signals require correction of both their inputs. The following steps outline the calibration procedure ...
  • Page 228 EM358x Parameter Performance INL (codes peak) 0.083 0.092 0.163 0.306 0.624 1.229 2.451 4.926 0.047 0.051 0.093 0.176 0.362 0.719 1.435 2.848 INL (codes RMS) DNL (codes peak) 0.028 0.035 0.038 0.044 0.074 0.113 0.184 0.333 0.008 0.009 0.011 0.014 0.019 0.029 0.048...
  • Page 229 EM358x Table 11-7. ADC Module Key Parameters for 6 MHz sampling Parameter Performance ADC_PERIOD Conversion Time (µs) 5.33 10.7 21.3 42.7 85.3 Nyquist Freq (kHz) 93.8k 46.9k 23.4k 11.7k 5.86k 2.93k 1.47k 3 dB Cut-off (kHz) 56.6k 28.3k 14.1k 7.07k 3.54k 1.77k INL (codes peak)
  • Page 230 EM358x 1.5 V. The differential measurements were done at f = 7.7% f , level = 1.2 V p-p swing and a common input Nyquist mode voltage of 1.5 V. Table 11-8. ADC Module Key Parameters for input buffer enabled and 6 MHz sampling Parameter Performance ADC_PERIOD...
  • Page 231 EM358x INL and DNL are referenced to a LSB of the Equivalent ADC Bits shown in the last row of Table 11-6. ENOB (effective number of bits) can be calculated from either SNR (signal to non-harmonic noise ratio) or SINAD (signal-to-noise and distortion ratio).

  • Page 232: Registers

    EM358x 11.6 Registers ADC_DATA ADC Data Register Address: 0x4000E000 Reset: 0x00000000 ADC_DATA_FIELD ADC_DATA_FIELD Bitname Bitfield Access Description ADC_DATA_FIELD [15:0] ADC conversion result. The result is a signed 2’s complement value. The significant bits of the value begin at bit 15 regardless of the sample period used.
  • Page 233 EM358x ADC_CFG ADC Configuration Register Address: 0x4000E004 Reset: 0x00001800 ADC_PERIOD ADC_CFGRSVD2 ADC_MUXP ADC_MUXP ADC_MUXN ADC_1MHZCLK ADC_CFGRSVD ADC_ENABLE Bitname Bitfield Access Description ADC_PERIOD [15:13] ADC sample time in clocks and the equivalent significant bits in the conversion. 0: 32 clocks (7 bits). 1: 64 clocks (8 bits).
  • Page 234 EM358x ADC_OFFSET ADC Offset Register Address: 0x4000E008 Reset: 0x0000 ADC_OFFSET_FIELD ADC_OFFSET_FIELD Bitname Bitfield Access Description ADC_OFFSET_FIELD [15:0] 16-bit signed offset added to the basic ADC conversion result before gain correction is applied. Rev. 0.4...
  • Page 235 EM358x ADC_GAIN ADC Gain Register Address: 0x4000E00C Reset: 0x8000 ADC_GAIN_FIELD ADC_GAIN_FIELD Bitname Bitfield Access Description ADC_GAIN_FIELD [15:0] Gain factor that is multiplied by the offset-corrected ADC result to produce the output value. The gain is a 16-bit unsigned scaled integer value with a binary decimal point between bits 15 and 14.
  • Page 236 EM358x ADC_DMACFG ADC DMA Configuration Register Address: 0x4000E010 Reset: 0x0 ADC_DMARST ADC_DMAAUTOWRAP ADC_DMALOAD Bitname Bitfield Access Description ADC_DMARST Write 1 to reset the ADC DMA. This bit auto-clears. ADC_DMAAUTOWRAP Selects DMA mode. 0: Linear mode, the DMA stops when the buffer is full. 1: Auto-wrap mode, the DMA output wraps back to the start when the buffer is full.
  • Page 237 EM358x ADC_DMASTAT ADC DMA Status Register Address: 0x4000E014 Reset: 0x0 ADC_DMAOVF ADC_DMAACT Bitname Bitfield Access Description ADC_DMAOVF DMA overflow: occurs when an ADC result is ready and the DMA is not active. Cleared by DMA reset. ADC_DMAACT DMA status: reads 1 if DMA is active. Rev.
  • Page 238 EM358x ADC_DMABEG ADC DMA Begin Address Register Address: 0x4000E018 Reset: 0x20000000 ADC_DMABEG ADC_DMABEG Bitname Bitfield Access Description ADC_DMABEG [15:0] ADC buffer start address. Caution: this must be an even address - the least significant bit of this register is fixed at zero by hardware. Rev.
  • Page 239 EM358x ADC_DMASIZE ADC DMA Buffer Size Register Address: 0x4000E01C Reset: 0x0 ADC_DMASIZE_FIELD ADC_DMASIZE_FIELD Bitname Bitfield Access Description ADC_DMASIZE_FIELD [14:0] ADC buffer size. This is the number of 16-bit ADC conversion results the buffer can hold, not its length in bytes. (The length in bytes is twice this value.) Rev.
  • Page 240 EM358x ADC_DMACUR ADC DMA Current Address Register Address: 0x4000E020 Reset: 0x20000000 ADC_DMACUR_FIELD ADC_DMACUR_FIELD Bitname Bitfield Access Description ADC_DMACUR_FIELD [15:1] Current DMA address: the location that will be written next by the DMA. Rev. 0.4...
  • Page 241 EM358x ADC_DMACNT ADC DMA Count Register Address: 0x4000E024 Reset: 0x0 ADC_DMACNT_FIELD ADC_DMACNT_FIELD Bitname Bitfield Access Description ADC_DMACNT_FIELD [14:0] DMA count: the number of 16-bit conversion results that have been written to the buffer. Rev. 0.4...
  • Page 242 EM358x INT_ADCFLAG ADC Interrupt Flag Register Address: 0x4000A810 Reset: 0x0 INT_ADCOVF INT_ADCSAT INT_ADCULDFULL INT_ADCULDHALF INT_ADCFLAGRSVD Bitname Bitfield Access Description INT_ADCOVF DMA buffer overflow interrupt pending. INT_ADCSAT Gain correction saturation interrupt pending. INT_ADCULDFULL DMA buffer full interrupt pending. INT_ADCULDHALF DMA buffer half full interrupt pending. INT_ADCDATA ADC_DATA register has data interrupt pending.
  • Page 243 EM358x INT_ADCCFG ADC Interrupt Configuration Register Address: 0x4000A850 Reset: 0x0 INT_ADCOVF INT_ADCSAT INT_ADCULDFULL INT_ADCULDHALF INT_ADCCFGRSVD Bitname Bitfield Access Description INT_ADCOVF DMA buffer overflow interrupt enable. INT_ADCSAT Gain correction saturation interrupt enable. INT_ADCULDFULL DMA buffer full interrupt enable. INT_ADCULDHALF DMA buffer half full interrupt enable. INT_ADCDATA ADC_DATA register has data interrupt enable.

  • Page 244: Trace Port Interface Unit (Tpiu)

    EM358x 12 Trace Port Interface Unit (TPIU) ® The EM358x integrates the standard ARM Trace Port Interface Unit (TPIU). The TPIU receives a data stream ® ® from the on-chip trace data generated by the standard ARM Instrument Trace Macrocell (ITM) and ARM Embedded Trace Macrocell (ETM), buffers the data in a FIFO for the ITM and FIFO for the ETM, formats the data, and serializes the data to be sent off chip through alternate functions of the GPIO.

  • Page 245: Instrumentation Trace Macrocell (Itm)

    EM358x 13 Instrumentation Trace Macrocell (ITM) ® The EM358x integrates the standard ARM Instrumentation Trace Macrocell (ITM). The ITM is an application- driven trace source that supports printf style debugging to trace software events and emits diagnostic system ® information from the ARM Data Watchpoint and Trace (DWT).

  • Page 246: Embedded Trace Macrocell (Etm)

    EM358x 14 Embedded Trace Macrocell (ETM) ® The EM358x integrates the standard ARM Embedded Trace Macrocell (ETM) version 3.4. The ETM is a powerful debug component that enables reconstruction of program execution. The ETM is designed as a high-speed, low-power debug tool that only supports instruction trace. The ETM generates information that trace software tools use to reconstruct the execution of all or part of a program.

  • Page 247: Data Watchpoint And Trace (Dwt)

    EM358x 15 Data Watchpoint and Trace (DWT) ® The EM358x integrates the standard ARM Data Watchpoint and Trace (DWT). The DWT provides hardware support for profiling and debugging functionality. The DWT offers the following features:  PC sampling  Comparators to support: Watchpoints –...

  • Page 248: Flash Patch And Breakpoint (Fpb)

    EM358x 16 Flash Patch and Breakpoint (FPB) ® The EM358x integrates the standard ARM Flash Patch and Breakpoint (FPB). The FPB implements hardware breakpoints. The FPB also provides support for remapping of specific instruction or literal locations from flash memory to an address in RAM memory. The FPB contains: ...

  • Page 249: Serial Wire And Jtag (Swj) Interface

    EM358x 17 Serial Wire and JTAG (SWJ) Interface The EM358x includes a standard Serial Wire and JTAG (SWJ) Interface. The SWJ is the primary debug and programming interface of the EM358x. The SWJ gives debug tools access to the internal buses of the EM358x, and allows for non-intrusive memory and register access as well as CPU halt-step style debugging.

  • Page 250: Register Address Table

    EM358x A. Register Address Table BLOCK CM_LV 40004000 - 4000403C CM_LV Address Name Type Reset Description 40004038 PERIPHERAL_DISABLE Peripheral Disable Register 4000403C RAM_RETAIN FFFF RAM Retention Register BLOCK INTERRUPTS 4000A000 - 4000AFFF Interrupts Address Name Type Reset Description 4000A800 INT_TIM1FLAG Timer 1 Interrupt Flag Register 4000A804 INT_TIM2FLAG...
  • Page 251 EM358x BLOCK GPIO 4000B000 - 4000BFFF General Purpose IO Address Name Type Reset Description 4000B000 GPIO_PACFGL 4444 Port A Configuration Register (Low) 4000B004 GPIO_PACFGH Port A Configuration Register (High) 4444 4000B008 GPIO_PAIN Port A Input Data Register 4000B00C GPIO_PAOUT Port A Output Data Register 4000B010 GPIO_PASET Port A Output Set Register...
  • Page 252 EM358x BLOCK SERIAL 4000C000 - 4000CFFF Serial Controllers Address Name Type Reset Description 4000C000 SC2_RXBEGA Receive DMA Begin Address Register A 20000000 4000C004 SC2_RXENDA 20000000 Receive DMA End Address Register A 4000C008 SC2_RXBEGB 20000000 Receive DMA Begin Address Register B 4000C00C SC2_RXENDB 20000000...
  • Page 253 EM358x BLOCK SERIAL 4000C000 - 4000CFFF Serial Controllers Address Name Type Reset Description 4000C83C SC1_DATA Serial Data Register 4000C840 SC1_SPISTAT SPI Status Register 4000C844 SC1_TWISTAT TWI Status Register 4000C848 SC1_UARTSTAT UART Status Register 4000C84C SC1_TWICTRL1 TWI Control Register 1 4000C850 SC1_TWICTRL2 TWI Control Register 2 4000C854...
  • Page 254 EM358x BLOCK TIM1 4000E000 - 4000EFFF General Purpose Timer 1 Address Name Type Reset Description 4000F000 TIM1_CR1 Timer 1 Control Register 1 4000F004 TIM1_CR2 Timer 1 Control Register 2 4000F008 TIM1_SMCR Timer 1 Slave Mode Control Register 4000F014 TIM1_EGR Timer 1 Event Generation Register 4000F018 TIM1_CCMR1 Timer 1 Capture/Compare Mode Register 1...
  • Page 255 EM358x BLOCK NVIC E000E000 - E000EFFF Nested Vectored Interrupt Controller Address Name Type Reset Description E000E100 INT_CFGSET Top-Level Set Interrupts Configuration Register E000E180 INT_CFGCLR Top-Level Clear Interrupts Configuration Register E000E200 INT_PENDSET Top-Level Set Interrupts Pending Register E000E280 INT_PENDCLR Top-Level Clear Interrupts Pending Register E000E300 INT_ACTIVE Top-Level Active Interrupts Register...
  • Page 256 EM358x OCUMENT HANGE Revision 0.1 to Revision 0.2  Information relocated from Ember EM358 Data Sheet  Updated GPT, ADC, and Interrupt registers  Removed references to serial controllers 3 and 4, and made associated changes to serial controller text. Revision 0.2 to Revision 0.3 ...
  • Page 257 Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur.

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