Sony SCD-C555ES Service Manual page 45

Pin No. Pin Name
61 VSS
62, 63 HCS0, HCS1
64 VDD
65 DASP
66 to 69 MDB0 to MDB3
70 VSS
71 MDB4
72 VDD5V
73 to 75 MDB5 to MDB7
76 XMWR
77 VDD
78 XRAS
79, 80 MA0, MA1
81 VSS
82 to 87 MA2 to MA7
88 VDD
89 MA8
90 VSS
91 MA9/MNT0
92 MA10/MNT1
93 MA11/MNT2
94 XMOE
95 XCAS
96, 97 MDB8, MDB9
98 VSS
99 MDBA
100 VDD
101, 102 MDBB, MDBC
103 VDD5V
104 to 106 MDBD to MDBF
107 GFS
108 VSS
109 APEO
110 VDD
111 DASYO
112 GNDA5
113, 114 ASF1, AFS2
115 DASYI
116 RFDCC
117 RF IN
118, 119 VCCA5, VCCA4
120 VCOR1
121 VCOIN
122, 123 GNDA4, GNDA3
124 LPF5
125 VC1
126, 127 LPF2, LPF1
128, 129 VCCA3, VCCA2
130 PDO
131 PDHVCC
I/O
— Ground terminal (digital system)
I Not used (open)
— Power supply terminal (+3.3V) (digital system)
I/O Not used (pull up)
I/O Two-way data bus with the D-RAM (IC706)
— Ground terminal (digital system)
I/O Two-way data bus with the D-RAM (IC706)
— Power supply terminal (+5V)
I/O Two-way data bus with the D-RAM (IC706)
O Write enable signal output to the D-RAM (IC706)
— Power supply terminal (+3.3V) (digital system)
O Row address strobe signal output to the D-RAM (IC706)
O Address signal output to the D-RAM (IC706)
— Ground terminal (digital system)
O Address signal output to the D-RAM (IC706)
— Power supply terminal (+3.3V) (digital system)
O Address signal output to the D-RAM (IC706)
— Ground terminal (digital system)
O Address signal output to the D-RAM (IC706)
O RF data signal output terminal for disc mark detection
Clock signal output terminal for disc mark detection
O
Monitor signal output to the CPU (IC901)
O Output enable signal output to the D-RAM (IC706)
O Column address strobe signal output to the D-RAM (IC706)
I/O Two-way data bus with the D-RAM (IC706)
— Ground terminal (digital system)
I/O Two-way data bus with the D-RAM (IC706)
— Power supply terminal (+3.3V) (digital system)
I/O Two-way data bus with the D-RAM (IC706)
— Power supply terminal (+5V)
I/O Two-way data bus with the D-RAM (IC706)
O Guard frame sync signal output to the CPU (IC901)
— Ground terminal (digital system)
O Absolute phase error signal output
— Power supply terminal (+3.3V) (digital system)
O RF binary signal output
— Ground terminal (analog system)
— Filter connected terminal for selection the constant asymmetry compensation
I Analog signal input after integrated from the RF binary signal
I Input terminal for adjusting DC cut high-pass filter for RF signal
I RF signal input from the CXD1881R (IC001)
— Power supply terminal (+3.3V) (analog system)
— VCO oscillating range setting resistor connected terminal
I VCO input terminal
— Ground terminal (analog system)
O Signal output from the operation amplifier from PLL loop filter
I Middle point voltage (+1.65V) input terminal
I Inverted signal input to the operation amplifier from PLL loop filter
— Power supply terminal (+3.3V) (analog system)
O Signal output from the charge pump for phase comparator
I Middle point voltage input terminal for RF PLL
Description
SCD-C555ES
45