Aaeon FSB-H81H Manual page 89

Full-size, intel core i7 / i5 / i3, lga 1150 processor, full-size cpu card, with ddr3 / l, 2 gigabit ethernet usb 3.0 / usb2.0, sata 6.0gb/s, sata 3.0 gb/s
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F u l l - s i z e S B C
Void aaeonWdtSetTimeoutCount(BYTE tTimeout){
f81866SetLdn(0x07);
f81866WriteByte(F81866_WDT_TIME_REG, tTimeout);
}
Void aaeonWdtSetEnable(BOOL bEnable){
f81866SetLdn(0x07);
if(bEnable){
f81866WriteByte(0x30, 0x01);
WDT_BASE_ADDR =
(f81866ReadByte(F81866_WDT_BASEADDR_REG_MSB) << 8)
| f81866ReadByte(F81866_WDT_BASEADDR_REG_LSB);
WDT_STATUS = f81866ReadByte(F81866_WDT_CONTROL_REG);
f81866WriteByte(F81866_WDT_CONTROL_REG, WDT_STATUS | 0x20);
WDT_STATUS = f81866ReadByte(F81866_WDT_PME_REG);
f81866WriteByte(F81866_WDT_PME_REG, WDT_STATUS | 0x01);
}else{
f81866WriteByte(0x30, 0x00);
WDT_BASE_ADDR = 0;
WDT_STATUS = f81866ReadByte(F81866_WDT_CONTROL_REG);
f81866WriteByte(F81866_WDT_CONTROL_REG, WDT_STATUS & 0xDF);
WDT_STATUS = f81866ReadByte(F81866_WDT_PME_REG);
f81866WriteByte(F81866_WDT_PME_REG, WDT_STATUS & 0xFE);
}
}
Appendix A Programming the Watchdog Timer
F S B - H 8 1 H
A-6

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