Chip Select Unit; Interrupt Controller; Bus Unit - Honeywell XK516D1 Maintenance Manual

Honeywell
COMPONENT MAINTENANCE MANUAL
PART NUMBER 964-0452
purposes, the crystal oscillator can be isolated from the processor by jumper,
X2. Functional units that are integrated in the processor are:
a Timers
The processor has 3 independent timers, which timers receive their clock pulse
from the processor clock. Two of the timers have a programmable output. All
timers can generate an interrupt.
Timer 0 – serves as a baud rate clock generator for both serial interfaces. A
symmetrical square-wave pulse with 16 times the baud rate of the serial inter-
faces is present at the timer output, that is 16 * 9600 = 153.6kHz.
Timer 1 – serves as a clock generator for the serial ARINC inputs and outputs.
A symmetrical rectangular pulse signal of 50kHz is present (C50KHZ).
Timer 2 – has no output line and is used as a time base for the operating system.
An interrupt is generated every 10ms. The operating system can derive
time-controlled operations from this interrupt.
b Chip Select Unit
The processor chip select unit permits direct actuation of memory blocks in the
processor. Separate signal lines are available for the memory and the I/O area.
The addressable area of the chip select signals is programmable. The lines are
assigned as shown in Fig. 25.
c Interrupt controller
The interrupt controller in the processor processes external and internal inter-
rupt requests, and branches the program to the appropriate interrupt routines,
provided that the interrupt is released and no interrupt with a higher priority is
currently being processed.
Five external interrupt inputs are available.
NM1 – Not in use
INT0 – CM interrupt input of the HF modules via the module bus
INT1 – Interrupt of serial interfaces test and coupler
INT2 – ARINC control input, ARINC BIT input, ARINC BIT output
INT3 – Parallel inputs
d Bus unit
The control signals for actuating the address and data drivers are generated in
the bus unit. Address lines A0 to A15 and controt line BHE are generated via
address latches D2, D3, and D4 from the multiplexed address data bus AD0 to
AD15 by means of control signal ALE.
Bidirectional data drivers, D5 and D6, are controlled by signals DEN and DT/R.
The DTIR signal states the data directionk, and signal DEN releases the data
Ω
driver. The data lines are connected to 5V via 10k resistors in each case.
e DMA controller
Not in use
Page 76
1I.B.1516A Page 50
23-12-01
Mar 30/01