Memory System Block Diagram; Output Block Diagram; Controller Block Diagram; Power Supply Block Diagram - Tektronix 5D10 Service Manual

MEMORY SYSTEM
BLOCK DIAGRAM
Figure 3-4 shows the Memory System Block Diagram .
Digital data from the Successive Approximation Register
(described above) feeds the Digitizer Output Register .
Binary control data from the microprocessor appears on
the Numbers (NO through N9) bus . These data include
start-point information for the waveform, read increment
information for the Time Register, and self test data . The
Memory Data Selector chooses between the numbers
input from the microprocessor or the digitizer output . The
Write Address Counter steps the write addresses in
sequence . The Write Address Modifier alters bits WO
through W2 from the counter when a reference
waveform has been saved .
The Memory Address Selector chooses write addresses
from the Write Address Counter and Write Address
Modifier, or read addresses from the Read Address
Register . These addresses go to the Waveform Memory,
the B Selector, and the Memory Data And Address
selector . The Memory
Data
And
Address selector
chooses either the waveform addresses or the Waveform
Memory output for data feedback to the microprocessor .
The Waveform Memory stores the binary data from the
digitizer . The output from the memory is applied to the X
and Y Display registers . The X display register also
displays output from the Time Register when the 5D10
operates in the Y-T mode (time for the X axis) .
The B Selector chooses either the output from the
Memory Address Selector or the Numbers bus and
directs them to the Adder . The Scratchpad saves the
write addresses for the trigger point and the last point on
each waveform . The output from the Scratchpad is added
to the B Selector output by the Adder and applied to the
Time Register and the Read Address Register . The A
Selector chooses either the Time Register or the Read
Address Register output for the A input to the Adder . All
of these elements together generate a sequence of read
addresses and time points used in displaying the stored
waveform, and provide information to the Loadstop Logic
circuitry used during acquisition . The Read and Write
Controller provides control signals for these blocks .
OUTPUT BLOCK DIAGRAM
Figure 3-5 shows the Output Block Diagram . Binary data
from the Waveform Memory passes to the X and Y
Display Registers . The Y Display Register is an eight-bit
REV APR 1985
Theory of Operation-5D10 Volume 1
register and the X Display Register is a 10-bit register, as
more data points are included in the X axis . The X And Y
Register Clocks update the contents of the display
registers . Outputs from the Display Registers feed the D
to A Converters .
The D to A Converters change the binary word (stored in
memory) to an analog voltage corresponding to the
position on the input waveform of the sampled voltage .
This voltage feeds the X and Y Output circuits . The X and
Y Output circuits amplify the voltage for the display in
dots, or integrate from the voltages representing the dots
for a continuous trace (JOIN DOTS) . The Display Timer
block determines the duration of the dot or vector display .
Blanking and unblanking of the crt is controlled through
circuitry in the mainframe and the Z axis circuitry . The
functions performed in the X and Y Output circuitry are
controlled by the Controller block .
CONTROLLER BLOCK DIAGRAM
Figure 3-6 shows the Controller Block Diagram . The CPU
block consists of an eight-bit microprocessor that obtains its
instructions from 16 k bytes of ROM . Also available is 1 k
byte of RAM . The Control Clock Oscillator provides timing
for the CPU and the waveform memory read and write con-
troller. The CPU outputs information to the instrument
through the I/O Control and the Controller Outputs . The in-
strument reports to the CPU, concerning its status and the
conditions of the front-panel controls, via the Front Panel
Switches and Machine States .
POWER SUPPLY BLOCK DIAGRAM
Figure 3-7 shows the Power Supply Block diagram . The
Oscillator circuitry generates a sawtooth waveform at a
frequency of about 100 kHz . This waveform feeds the
Comparator
block along with voltage and
current
information from the Voltage Regulator . The output from
the Comparator is a varying-duty-cycle square wave
depending on the voltage or current demands from the
power supply . The Comparator output feeds the Gate
Driver circuitry . This circuitry drives the switching
transistors in the Switching Transistor And Transformer
block providing input for the transformer . The output
from this block drives the Rectifiers, Filters And Current
Senses block . The Protection block prevents carnage to
the power supply from fault conditions-
3-5