Figure 4. Setup And Hold Timing Diagram; Table 5. Setup And Hold Timing - Planar ICEBrite EL VGA Displays EL640.480-AM User Manual

S (FRAME)
CP1 (LINE)
tCLK
tCL tCH
CP2 (SHIFT)
UD0 to UD3
LD0 to LD3

Figure 4. Setup and Hold Timing Diagram.

Table 5. Setup and Hold Timing.

Symbol Name
tS21 CP1 allowance from CP2
tS12 CP2 allowance from CP1
tS3 CP1 allowance to CP2
tSU Setup time
tHOLD Hold time
tR Rise time
tF Fall time
tCLK CP2 clock cycle
tCL CP2 clock low time
tCH CP2 clock high time
Input signals UD0 through UD3 contain the video data for the upper screen
and signals LD0 through LD3 contain the data for the lower screen. For
example, four pixels (UD3:1,1–UD0:1,1) are sent to row 1 at the same time as
four pixels (LD0:1,1–LD3:1,1) are sent to row 241. This results in eight pixels
sent on each cycle of video clock CP2. Pixel information is supplied from left to
right and from top to bottom. Video data for one row is latched on the fall of
CP1 (Figure 5).
tR
tS21
tR tF
tSU tHOLD
Min.
0
200
50
50
40
154
60
60
EL640.480-AM Operations Manual (020-0351-00C)
tSU tHOLD
tF
tS12
tS3
Max Unit
ns
ns
ns
ns
ns
30 ns
30 ns
ns
ns
ns
11