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Surface Concept Delayline DLD 8080 Manual

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Delayline Detector
DLD 8080
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  • Page 1 Delayline Detector DLD 8080 Manual...
  • Page 3 All rights reserved. No part of this manual may be reproduced without the prior permission of Surface Concept GmbH. Surface Concept GmbH Am Sägewerk 23a 55124 Mainz Germany Tel. ++49 6131 62760 Fax: ++49 6131 6271629 www.surface-concept.com, support@surface-concept.de Manual Version: 1.2...

  • Page 5: Table Of Contents

    Table of Contents Table of Contents ....................................5 Introduction......................................8 General Information ................................... 8 Safety Instructions..................................8 General Overview of the System ............................9 Installation ......................................10 Initial Inspection ..................................10 Installation ....................................11 3.2.1 Mounting the delayline detector..........................11 3.2.2 Detector Orientation ..............................
  • Page 6 Delayline Detector - Vacuum Wiring ..........................21 Delayline Detector – Connection Ports ......................... 22 Pulse Processing Electronics ............................... 24 Pulse Processing Electronics ACU 3.4.2........................24 7.1.1 Positions of the Discriminator Threshold Regulators ................... 25 Time-to-Digital-Converter (TDC) ..............................26 Schematic Description of the USB2.0-TDC ......................... 26 Basic Operation Modes of the GPX TDC Chip......................
  • Page 7 11.3 Operation ....................................41 Technical Data ....................................42 List of Figure....................................43...

  • Page 8: Introduction

    Introduction 2.1 General Information This manual is intended to assist users in the installation, operation and maintenance of the Delayline Detector DLD 8080. It is divided into 13 chapters. The chapter “Introduction” contains a brief description of the DLD. The chapter “Installation” refers to installation and cabling. One chapter describes the USB driver installation.

  • Page 9: General Overview Of The System

    2.3 General Overview of the System The Surface Concept delayline detectors are particularly developed for the needs of 1D(x), 2D(x,t), 2D(x,y) or 3D(x,y,t) area and time detection of electrons, ions, x-ray and UV-light as well as for multi hit detection of high rates with the 4-quadrant detector systems.

  • Page 10: Installation

    Visual inspection of the system is required to ensure that no damage has occurred during shipping. Should there be any signs of damage, please contact SURFACE CONCEPT immediately. Please check the delivery according to the packing list (see Table 1) for completeness.

  • Page 11: Installation

    Installation 3.2.1 Mounting the delayline detector The detector is transported under vacuum. Vent the transport container carefully and release the M8 screws of the vacuum container and pull out the detector carefully. Check the front side of the MCP stack for particles. The microchannel plates in front of the detector should be protected from exposure to particle contamination.

  • Page 12: Cabling And High Voltage

    Figure 2: 0/0 position of the DLD image (black dot). 3.2.3 Cabling and High Voltage The general connection scheme of the delayline detector including its readout package is shown in Figure 3. Figure 3: Connection scheme of the delayline detector and readout package. •...
  • Page 13 Start” to apply standard TTL signals. The start input of the TDC is not working with start signals of frequencies smaller 25 kHz and larger than 7 MHz. Larger start pulse frequencies must be divided down with an appropriate frequency divider (e.g. divider with factor of 16 for 80 MHz start pulse frequency).

  • Page 14: Recommended System Requirements

    Finish the complete cabling before the TDC is turned on and the GUI monitor software is started. Also, close the software and turn off the TDC before performing any changes to the cabling. This applies especially to the connection and disconnection of the start input of the TDC.

  • Page 15: Usb 2.0 Driver Installation

    USB 2.0 Driver Installation • First, log on as Administrator. Close all applications on your PC. If you are using any anti-virus or firewall software, close them (or disable them). Connect the USB cable to your Windows System with USB2.0 enabled. Windows will find the new hardware, and the "Found New Hardware Wizard" will launch.
  • Page 16 • Continue Installation although the Windows XP capability test failed. • Enter the path where the driver is located (or Browse to it) • The internal name of the USB2.0 TDC driver is “ceusb3.sys”, select it and press “Open”.
  • Page 17 • To continue, click "OK". The driver for the Surface Concept USB2.0 TDC will be installed. • After a few seconds, a finishing dialog should appear as below. To finish, click "Finish". After finishing the installation routine for the first time, it will start again. Go through the routine again a second time completely.

  • Page 18: Dld - Principle Of Operation

    DLD - Principle of Operation Basics of Delayline Detection A delayline detector (DLD) consists of a microchannel plate array for pulse amplification and an in-vacuum detection unit consisting of a meander structured delayline (DLD anode). Each hit position is encoded by a fast data acquisition unit, which also may detect the hit time referenced to an external clock in repetitive (stroboscopic) experiments.

  • Page 19: Basic Operational Modes Of The Delayline Detector

    the DLD meander (positive potential difference between anode and back side of MCP stack) where it induces electrical pulses in the delayline by capacitive coupling. The pulses are traveling to the both ends of the meander within a time determined by the hitting position. The average time at both ends of the meander relative to an external repetitive clock generates the time coordinate if required.

  • Page 20: Data Acquisition

    Data Acquisition Each readout line of the detector anode is connected to a fast amplifier followed by a constant fraction discriminator (CFD) for pulse shaping. They are encapsulated inside the pulse processing electronics (ACU = Amplifier-CFD-Unit or AU = Amplifier-Unit). The main function of the CFD is digital pulse discrimination, ideally without any time-walk even at varying pulse heights.

  • Page 21: Delayline Detector Layout

    Delayline Detector Layout Delayline Detector - Vacuum Wiring The delayline detector consists of a detection area, defined by the detector cover, the MCP holders and the detector anode. The detector anode consists of two meander structured delaylines (named x and y), which are placed above each other (electrically isolated) and are oriented perpendicular to each other.

  • Page 22: Delayline Detector - Connection Ports

    Delayline Detector – Connection Ports The delayline detector carries two single SHV feed-throughs for the high voltage supply on a CF 40 flange and a second CF 40 flange, which holds 4 SMB feed-throughs for signal transfer of the meander. The flange for the signal transfer also holds an orientation pin for correct orientation of the ACU.
  • Page 23 The resistance between F and A (resistance of MCP stack incl. internal resistance) should be in the range of 12 – 45 MΩ (the exact value is given in the specification sheet of your detector),...

  • Page 24: Pulse Processing Electronics

    Pulse Processing Electronics The pulse processing electronics ACU (Amplifier-CFD-Unit) and AU (Amplifier-Unit) hold all devices like the amplifiers, pulse shapers, and constant fraction discriminators to turn the analogue pulses from the detector into digital pulses suitable for the Time-to-Digital Converter. Pulse decoupling is either performed within the pulse processing electronics or directly in-vacuum, depending on detector type and layout.

  • Page 25: Positions Of The Discriminator Threshold Regulators

    The readout electronics is adjusted to its best performance to the operation voltage of the detector when delivered. Do not change the adjustment at all. Changing the adjustment can easily end up with a status, where a readjustment must be made by Surface Concept. Y1 Y2 Amplification Regulator Fraction Regulator...

  • Page 26: Time-To-Digital-Converter (Tdc)

    Time-to-Digital-Converter (TDC) Schematic Description of the USB2.0-TDC The USB2.0-TDC serie combines the excellent performance of the GPX TDC chip (ACAM GmbH) with a field programmable gate array (FPGA) and a high speed USB interface, either in the design with a single GPX chip (USB2.0-TDC) or with two GPX chips (Double USB2.0-TDC) operated in I-mode with 82 ps bin size or with one (Dual Channel USB2.0-TDC) or two GPX chips (Quad Channel USB2.0-TDC) operated in R-mode with 27 ps time bin or G-mode with 36 ps time bin.

  • Page 27: Basic Operation Modes Of The Gpx Tdc Chip

    acquisition process. The FPGA also sends out the synchronization pulse for marking the end of an acquisition (Sync. Out). The TDC data streaming can be performed as measured (RawData mode) or including a DLD specific data pre-conditioning (Pair mode). This concerns a channel pairing and a pair result arithmetic, a modulo arithmetic and many more.

  • Page 28: Layout Of The Quad Channel Usb2.0-Tdc

    Layout of the Quad Channel USB2.0-TDC 1. TDC Power socket 2. BNC sockets trigger synchronization IN and OUT 3. HDMI socket for DLD readout cable from ACU 4. USB 2.0 connection socket 5. BNC socket for TDC start input 6. Power switch to turn the TDC ON/OFF.

  • Page 29: Line Input

    8.3.3 Line Input Electrical Input (LINE): 85 V – 260 V, 50/60 Hz Power: 100 Watt (max.) Fuse: 1x T 1.6 A Interface (PC) and Software All operation functions of the USB2.0-TDCs for data readout of the detector package are encapsulated in the dynamic linked library “delayline.dll”.

  • Page 30: Dual Hv Supply

    Dual HV Supply This device produces lethal high voltage up to +5 kV. Hazardous voltages are present. Therefore only persons with the appropriate training are allowed to carry out the installation. Adjustment and repair work is only allowed to be carried out by SURFACE CONCEPT.

  • Page 31: Layout Of Dual Hv Supply & The Hv Filterbox

    Increase the high voltage very carefully, especially when the detector is used for the first time after installation or has been vented before. Strictly, follow the “Start-Up” procedure described in chapter 10.2. High voltage sparks may damage the meander or the MCPs seriously. Do not disconnect the SHV cables, while high voltage is applied to the delayline detector.

  • Page 32: Line Input Of Dual Hv Supply

    HV Filterbox A, F : High voltage inputs and outputs via SHV sockets from To DLD HV Supply Figure 12: Layout of the Dual HV Supply & HV filterbox 9.1.1 Line Input of Dual HV Supply Electrical Input (LINE): 230 V, 50 Hz Power: 28 Watt (max.) Fuse:...
  • Page 33 Figure 14: Detector anode grounded and operation voltage between F & A. Figure 15: Positive bias voltage applied to the front side of the MCP stack. The operation voltage between F & A is unchanged.
  • Page 34 Figure 16: Negative bias voltage applied to the front side of the MCP stack. The operation voltage between F & A is unchanged. Figure 17: Positive bias voltage applied to the detector anode. The operation voltage between F & A is unchanged.
  • Page 35 Figure 18: Negative bias voltage applied to the detector anode. The operation voltage between F & A is unchanged.

  • Page 36: Operation Of The Dld

    If sparking occurs, turn down the high voltage immediately and wait some time (up to 5 min.). Start the “Start-Up” procedure again with an increased ramp time. Is it not be possible to reach the operation voltage without sparking, then turn off the high voltage, stop the procedure and call SURFACE CONCEPT for further assistance.

  • Page 37: Start-Up" Procedure (For New Systems And For Systems, After Being Vented)

    This specified voltage is given in the specification sheet of the detector. There you also find a maximum operation voltage. Never exceed this voltage. Stick to the voltages given in the specification sheet. Contact Surface Concept before any other – especially higher – voltages are applied to the detector.

  • Page 38: Standard Start Procedure

    • After high voltage has been applied to the detector, check the detector output by means of the GUI software. The dark count rate without any source should correspond to the value given in the specification sheet. • Now you may start carefully with an electron/ light source observing the detector output. Keep in mind the description about the important operation details in chapter 5.4.

  • Page 39: Bake Out Procedure

    10.3 Bake Out Procedure The maximum allowed temperature for the detector is 150°C. Do not exceed this temperature. • Please read the bake out instruction completely and carefully, before starting the bake out procedure. • Windows and feed-throughs should be wrapped with aluminum foil, to protect them from rapid temperature changes.

  • Page 40: Microchannel Plate (Mcp)

    Microchannel Plate (MCP) Contact SURFACE CONCEPT before performing a replacement. Take care to note the orientation of the MCPs. The channels in the MCPs include a certain angle against the surface normal to the plate and the MCPs must be mounted in a chevron or z-stack configuration (depending on no.

  • Page 41: Operation

    Voltages must not be applied to the device while at atmospheric pressure. The pressure should be 1 x 10 mbar or lower at the microchannel plate before applying voltage. Otherwise, damaging ion feedback or electrical breakdown will occur. 11.3 Operation •...

  • Page 42: Technical Data

    Technical Data Delayline detector General: HV capability: none ∅ 80 mm round Active area: Operation voltage at detector: see specification sheet Max. voltage at DLD: see specification sheet Max. bias voltage: +/- 1700 V (depending on cabling) Max. bake-out temperature: 150°C Vacuum pressure range for operation: <...

  • Page 43: List Of Figure

    List of Figure Figure 1: Contents of delivery package .............................. 10 Figure 2: 0/0 position of the DLD image (black dot)........................12 Figure 3: Connection scheme of the delayline detector and readout package..............12 Figure 4: Principle of the 3D (x, y, t) delayline operation......................18 Figure 5: Schematic orientation and naming of the two meander structured delaylines.
  • Page 44 Control and Laboratory Use Issued on 01. February 2008 For and on behalf of Surface Concept GmbH This declaration does not represent a commitment to features or capabilities of the instrument. The safety notes and regulations given in the product related documentation must be observed at all times.
  • Page 45 Control and Laboratory Use Issued on 01. February 2008 For and on behalf of Surface Concept GmbH This declaration does not represent a commitment to features or capabilities of the instrument. The safety notes and regulations given in the product related documentation must be observed at all times.

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