JVC XV-S500BK Service Manual page 44

XV-S500BK/XV-S502SL
SST39VF160-7CEK (IC509) : 16M EEPROM
1. Pin layout
A15 1 48
A14 2 47
A13 3 46
A12 4 45
A11 5 44
A10 6 43
A9 7 42
A8 8 41
A19 9 40
NC 10 39
/WE 11 38
/RST 12 37
NC 13 36
NC 14 35
R/B 15 34
A18 16 33
A17 17 32
A7 18 31
A6 19 30
A5 20 29
A4 21 28
A3 22 27
A2 23 26
A1 24 25
2. Block diagram
A19~A0
/CE
/OE
/WE
3. Pin function
Symbol Pin name
A19~A0 Address Inputs
DQ15~DQ0 Data Input/Output
/CE Chip Enable
/OE Output Enable
/WE Write Enable
VCC Power Supply
Vss Ground
NC No Connection
1-44
A16
/BYTE
Vss
D15
D7
D14
D6
D13
D5
D12
D4
VCC
D11
D3
D10
D2
D9
D1
D8
D0
/OE
Vss
/CE
A0
X-Decoder
Address Buffer & Latches
Control Logic
To provide memory addresses. During sector erase A19~A11 address
lines will select the sector. During block erase A19~A15 address lines
will select the block.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are
in tri-state when /OE or /CE is high.
To activate the device when /CE is low.
To gate the data output buffers.
To control the write operations.
To provide 3-volt supply ( 2.7V-3.6V ).
16,777,216Bit
EEPROM
Cell Array
Y-Decoder
I/O Buffers & Data Latches
DQ15~DQ0
Function