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Typical Application (continued)
9.2.3 Application Curve
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating
Each V
pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
CC
supply, a 0.1-μF capacitor is recommended and if there are multiple V
capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs must not ever float. In many cases, functions or parts of functions of
digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3
of the 4 buffer gates are used. Such input pins must not be left unconnected because the undefined voltages at
the outside connections result in undefined operational states. Specified below are the rules that must be
observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low
bias to prevent them from floating. The logic level that should be applied to any particular unused input depends
on the function of the device. Generally they will be tied to GND or V
convenient.
11.2 Layout Example
V
CC
Unused Input
Input
Copyright © 1999–2015, Texas Instruments Incorporated
1600
Icc 1.8V
Icc 2.5V
1400
Icc 3.3V
Icc 5V
1200
1000
800
600
400
200
0
0
20
Figure 5. I
Conditions.
Output
Figure 6. Layout Diagram
Product Folder Links:
SCES210O – APRIL 1999 – REVISED DECEMBER 2015
40
60
Frequency - MHz
vs Frequency
CC
CC
, whichever make more sense or is more
CC
Input
Unused Input
SN74LVC2G241
SN74LVC2G241
80
D001
pins then a 0.01-μF or 0.022-μF
Output
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11
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