Texas Instruments SN74LVC2G241 Manual

SN74LVC2G241 Dual Buffer and Driver With 3-State Outputs

1 Features

• Available in the Texas Instruments
1
NanoFree™ Package
• Supports 5-V V Operation
CC
• Inputs Accept Voltages to 5.5 V
• Max t of 4.1 ns at 3.3 V
pd
• Low Power Consumption, 10-µA Maximum I
• ±24-mA Output Drive at 3.3 V
• Typical V (Output Ground Bounce)
OLP
<0.8 V at V = 3.3 V, T
CC
• Typical V (Output V
OHV
>2 V at V = 3.3 V, T
CC
• I Supports Live Insertion, Partial-Power-Down
off
Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate
Inputs From a Max of 5.5 V Down
to the V Level
CC
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

2 Applications

• AV Receivers
• Blu-ray Players and Home Theaters
• DVD Recorders and Players
• Desktop or Notebook PCs
• Digital Radio or Internet Radio Players
• Digital Video Cameras (DVC)
• Embedded PCs
• GPS: Personal Navigation Devices
• Mobile Internet Devices
• Network Projector Front-Ends
• Portable Media Players
• Pro Audio Mixers
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
CC
= 25°C
A
Undershoot)
OH
= 25°C
A
Tools &
Technical
Software
Documents
SCES210O – APRIL 1999 – REVISED DECEMBER 2015

3 Description

This dual buffer and line driver is designed for 1.65-V
to 5.5-V V operation.
CC
The SN74LVC2G241 device is designed specifically
to improve both the performance and density of 3-
state memory-address drivers, clock drivers, and bus-
oriented receivers and transmitters.
NanoFree package
breakthrough in IC packaging concepts, using the die
as the package.
The SN74LVC2G241 device is organized as two 1-bit
line drivers with separate output-enable (1OE, 2OE)
inputs. When 1OE is low and 2OE is high, the device
passes data from the A inputs to the Y outputs. When
1OE is high and 2OE is low, the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up
or power down, OE should be tied to V
pullup resistor, and OE should be tied to GND
through a pulldown resistor; the minimum value of the
resistor is determined by the current-sinking or the
current-sourcing capability of the driver.
This device is fully specified for partial-power-down
applications using I
outputs, preventing
through the device when it is powered down.
Device Information
PART NUMBER
SN74LVC2G241DCT SM8 (8)
SN74LVC2G241DCU VSOOP (8)
SN74LVC2G241YZP
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1
1OE
2
1A
7
2OE
5
2A
Support &
Community
SN74LVC2G241
technology is a
through a
CC
. The I circuitry disables the
off off
damaging current
(1)
PACKAGE BODY SIZE (NOM)
2.95 mm × 2.80 mm
2.30 mm × 2.00 mm
DSBGA (8) 1.91 mm × 0.91 mm
6
1Y
3
2Y
major
backflow