Yamaha DCU5D Service Manual page 33

Q P O
Q Q
BLOCK DIAGRAM 001 (DCU5D) 3 7 6 3 1 5 1 5 0
EXT DC INPUT
1P: GND
4P: 12V
+12V
JK1
AC/DC
CN1
FL301
+16V
VH
2P
GND
+3.3D
AC IN
Power LED
+3.3D
LD501
CN501 CN4
SW501
PH PH
RESET
3P 3P
SW
LED
T E
L 1 3 9 4 2 2 9 6 5 1 3
10,11,24-31,
36-41,44-47,
IC6
(208P)
53-58 198 /MUTE
Mute Control
CPU I/F
PLLP2
Address
8,9,14-18 Decode
EXTWC256
131
256OUT_ES
w w w
.
DM
28CA1-2001017464-1
http://www.xiaoyu163.com
N M L K
Power LED
+3.3D
LD1
IC1
+5D
About 1A
(25P)
（約1A）
DC-DC
Module
+3.3D About 2A
+3.3D
IC2
（約2A） (120P)
88 89
X1
TX0 RX0
22.1184MHz
MAIN CPU
IC300 H8S/2215R
IC302 74,76
(20P)
69
Q0 FWE 37
LATCH
D0
77
MD2 Flash: 256KB
LE
RAM: 20KB +3.3D
68
MD1
MODE6
90 67
P32
MD0
31 TX2 TX1 91
IC301 /RES 32 RX2 RX1 92
72
/SYSRES
SYSTEM
RESET
2
IC3
(5P)
2
IC5
MSYNC, MWC, M64, M128, M256
WC_CASI, 49M, /M LOCKSEL, /LOCKRTN
+3.3D
+5D
DBL RST
Clock System
OSC
120
X2
49MHz
SELECT
INTCLK
/DIVIDE
119 OSC
X3
45MHz
196 /MLOCK_SEL
Unlock
WCKSEL
Delay
191 /LOCKRTN
IC10
+5D
(14P)
PLL
96/88k
TLC2932
PLL
48/44k
DIR2
IC11
(44P)
x a o u 1 6 3
y
i
J I H G
8
A0–A7, D8–D15,
/CS_ES, /RD, /HWR, /RES_ES,
/IRQ_ES
4ch/LINE
8 ESID[0–7]
8 ESOD[0–7]
4ch/LINE
MWC, M256, M128
/MUTE_ES
256OUT_ES
Q Q
3 7 6 3 1
4ch/LINE 2ch/LINE
+3.3D
ESOD0 50
PASO_0 IC12
38-41 4 CIMIX_1–8
ESOD1 51 (144P) PASI_0–3
PASO_2
ESOD2 77
PBSO_0
59-62 4 CIMIX_9–16
ESOD3 79
PBSI_0–3
PBSO_2
ESOD4
103
PCSO_0
ATSC2A
ESOD5 89,92-94 4 CIMIX_17–24
105
PCSO_2 PCSI_0–3
ESOD6 132
PDSO_0
CISTM_A,B
ESOD7 134
119-122 4 CICUE A,B
PDSO_2 PDSI_0–3
256_CASIN
M256
MSYNC, MS256 M256
CIN_SYNC
MSYNC RES MUTE MSYNC
CIN_LOCK
+3.3D
4cH/LIEN
2ch/LINE
ESID0 38 IC13
PASI_0
50-53 4 COMIX_1–8
(144P)
ESID1 40 PASO_0–3
PASI_2
ESID2 59
PBSI_0
77-80 COMIX_9–16
4
ESID3 61
PBSO_0–3
PBSI_2
ESID4 89
ATSC2A 103-106 4 COMIX_17–24
PCSI_0
PCSO_0–3
COSTM_A,B
ESID5 93
PCSI_2
132-135 COCUE A,B
4
ESID6 PDSO_0–3
119
PDSI_0
ESID7 121
PDSI_2
MSYNC, MS256
MSYNC, MS256
MSYNC MSYNC
M256 RES MUTE M256
75
c o
.
F E D C
2 4
9 9 8
+3.3D +5D
SCI:230.4Kbps
CN8
ES
CN001
CASCADE
LD001
AVDM Module IN
LD002
CN006
JK003
200Pin
LD003
LD004 OUT
CN002
JK004
CN7
D0–D15, A1, A2, /CS_PLD, /RD, /HWR,
/LWR, SYSRES, CPUCLK
WC_CASI, 49M, /MLOCKSEL, LOCKRTN
IC16
(100P)
CPLD
PLL
CASCADE
IN
TLC2932
5 1 5 0 8 9 2 4 9
IC20
(14P)
CN5
+5D (68P)
IC35
MWC
(16P)
CASINTX
x1
Line
RTSOUT
Driver
+5D
CASCADE IN
CASINRX IC36-40
(16P)
x5
Line
CASI_WCIN
Receiver
D0–D6 IN_ID0–IN_ID6
Buffer
IC26
32ch IN
(20P)
/INIORD
CN6
(68P)
+5D
CASO_WCIN
IC46
(16P)
CASOUTRX
x1
Line
RTSIN
Receiver
+5D
IC41-45
CASOUTTX CASCADE OUT
(16P)
x5
Line
MWC
Driver
D0–D6 OUT_ID0–OUT_ID6
Buffer
IC27
32ch OUT
(20P)
/OUTIORD
m
BLOCK DIAGRAM 001 (DCU5D)
B A
2
9 9
DCU5D
1
2
3
4
5
6
8 2 9 9
7
8
9
10
11
12
3