Mbcg61594-130-E1 (X3299A00) Atsc2A - Yamaha DCU5D Service Manual

QQ
3 7 63 1515 0

MBCG61594-130-E1 (X3299A00) ATSC2A

PIN
NAME I/O
NO.
1 V
DD
2 XTST I
3 V
SS
4 WT_X I
5 RD_X I
6 CS_X I
7 HS_SEL I
8 RES_X I
9 V
SS
10 ADD[0] I
11 ADD[1] I
12 ADD[2] I
13 ADD[3] I
14 ADD[4] I
15 ADD[5] I
16 ADD[6] I
17 ADD[7] I
18 V
DD
19 V
SS
20 DAT[0] I/O
21 DAT[1] I/O
22 DAT[2] I/O
23 DAT[3] I/O
24 V
DD
25 V
SS
26 DAT[4] I/O
27 DAT[5] I/O
28 DAT[6] I/O
29 DAT[7] I/O
TE
L 13942296513
30 V
SS
31 V
DD
32 PA_I_H_MODE[0] I
33 PA_I_H_MODE[1] I
34 PA_I_H_MODE[2] I
35 PA_O_H_MODE[0] I
36 PA_O_H_MODE[1] I
37 PA_O_H_MODE[2] I
38 PA_SI0_ATI I
39 PA_SI1 I
40 PA_SI2 I
41 PA_SI3 I
42 PA_I_SW_SEL I
43 PA_SYNC_WC_SI I
44 PA_FS256_SI I
45 V
SS
46 PA_FS256_SO I
47 PA_SYNC_WC_SO I
48 PA_O_SW_SEL I
49 V
SS
50 PA_SO0 O
51 PA_SO1 O
52 PA_SO2 O
53 PA_SO3 O
54 V
DD
55 V
SS
56 PA_CLK_ATI I
57 PA_H_M4_SEL I
58 PA_O_MUTE I
59 PB_SI0 I
60 PB_SI1 I
61 PB_SI2 I
62 PB_SI3 I
63 PB_I_SW_SEL I
www
64 PB_SYNC_WC_SI I
65 PB_FS256_SI I
66 V
SS
67 PB_FS256_SO I
68 PB_SYNC_WC_SO I
.
69 PB_O_SW_SEL I
70 PB_I_H_MODE[0] I
71 PB_I_H_MODE[1] I
72 PB_I_H_MODE[2] I
http://www.xiaoyu163.com
FUNCTION
Power supply +3.3V
LSI test pin
Ground
CPU interface write input
CPU interface read input
CPU interface chip select input
Chip active select
System reset input
Ground
CPU interface address bus
Power supply +3.3V
Ground
CPU interface data bus
Power supply +3.3V
Ground
CPU interface data bus
Ground
Power supply +3.3V
Port A audio data input mode select
Port A audio data output mode select
Port A audio data input
Port A audio data input sync/wc select
Port A audio data input sync/wc input
Port A audio data input bit clock input (256fs)
Ground
Port A audio data output bit clock input (256fs)
Port A audio data output sync/wc input
Port A audio data output sync/wc select
Ground
Port A audio data output
Power supply +3.3V
Ground
Port A ADAT clock input
Port A audio data input buffer active select
Port A mute
Port B audio data input
Port B audio data input sync/wc select
Port B audio data input sync/wc input
Port B audio data input bit clock input (256fs)
x ao u163
y
Ground
Port B audio data output bit clock input (256fs)
Port B audio data output sync/wc input
i
Port B audio data output sync/wc select
Port B audio data input mode select
2 9
8
PIN
NAME I/O
NO.
73 V
DD
74 PB_H_M4_SEL I
75 PB_O_MUTE I
76 V
SS
77 PB_SO0_ATO O
78 PB_SO1 O
79 PB_SO2 O
80 PB_SO3 O
81 V
SS
82 PB_O_H_MODE[0] I
83 PB_O_H_MODE[1] I
84 PB_O_H_MODE[2] I
85 PC_I_H_MODE[0] I
86 PC_I_H_MODE[1] I
87 PC_I_H_MODE[2] I
88 PC_H_M4_SEL I
89 PC_SI0_ATI I
90 V
DD
91 V
SS
92 PC_SI1 I
93 PC_SI2 I
94 PC_SI3 I
95 PC_I_SW_SEL I
96 PC_SYNC_WC_SI I
97 PC_FS256_SI I
98 V
SS
99 PC_FS256_SO I
100 PC_SYNC_WC_SO I
Q Q 101 PC_O_SW_SEL I
3 6 7 1 3 1 5
102 V
SS
103 PC_SO0 O
104 PC_SO1 O
105 PC_SO2 O
106 PC_SO3 O
107 V
SS
108 PC_O_MUTE I
109 PC_O_H_MODE[0] I
110 PC_O_H_MODE[1] I
111 PC_O_H_MODE[2] I
112 PC_CLK_ATI I
113 V
SS
114 PD_I_H_MODE[0] I
115 PD_I_H_MODE[1] I
116 PD_I_H_MODE[2] I
117 V
SS
118 PD_H_M4_SEL I
119 PD_SI0 I
120 PD_SI1 I
121 PD_SI2 I
122 PD_SI3 I
123 PD_I_SW_SEL I
124 PD_SYNC_WC_SI I
125 PD_FS256_SI I
126 V
DD
127 V
SS
128 PD_FS256_SO I
129 PD_SYNC_WC_SO I
130 PD_O_SW_SEL I
131 V
SS
132 PD_SO0_ATO O
133 PD_SO1 O
134 PD_SO2 O
135 PD_SO3 O
136 V
SS
137 PD_O_MUTE I
co
138 V
SS
139 PD_O_H_MODE[0] I
140 PD_O_H_MODE[1] I
.
141 PD_O_H_MODE[2] I
142 XSM I
143 PA_WC_ATI O
144 PC_WC_ATI O
9 4 2 8
DM: IC12, 13
FUNCTION
Power supply +3.3V
Port B audio data input buffer active select
Port B mute
Ground
Port B audio data output
Ground
Port B audio data output mode select
Port C audio data input mode select
Port C audio data input buffer active select
Port C audio data input
Power supply +3.3V
Ground
Port C audio data input
Port C audio data input sync/wc select
Port C audio data input sync/wc input
Port C audio data input bit clock input (256fs)
Ground
Port C audio data output bit clock input (256fs)
Port C audio data output sync/wc input
Port C audio data output sync/wc select
0 5 8 2 9 9 4 2 8
Ground
Port C audio data output
Ground
Port C mute
Port C audio data output mode select
Port C ADAT clock input
Ground
Port D audio data input mode select
Ground
Port D audio data input buffer active select
Port D audio data input
Port D audio data input sync/wc select
Port D audio data input sync/wc input
Port D audio data input bit clock input (256fs)
Power supply +3.3V
Ground
Port D audio data output bit clock input (256fs)
Port D audio data output sync/wc input
Port D audio data output sync/wc select
Ground
Port D audio data output
m
Ground
Port D mute
Ground
Port D audio data output mode select
LSI test pin
Port A ADAT word clock output
Port C ADAT word clock output
DCU5D
9 9
9 9
13