Block Diagram - Video Control Section - Sony BDP-CX7000ES Service Manual

BDP-CX7000ES
6-2.
(Page 31)
(Page 34)
(Page 31)
(Page 35)
BDP-CX7000ES

BLOCK DIAGRAM - VIDEO CONTROL Section -

8
E3P_Y2 – 9
8
E3P_C2 – 9
E3P_HD
E3P_VD
E3P_VCK
CLOCK BUFFER
IC101
X201
20MHz
A
I2C_400k_SDA
I2C_400k_SCL
KYOTO_XRST
GLB_XRST
GLUE_XCS
HDE1_XCS
HDE2_XCS
BUFFER
IC105
CSI_DO
8 IN7 OUT7 12
CSI_DI
11 OUT8 IN8 9
CSI_CK
6 IN5 OUT5 14
EMMA_CSI0_CKO
E
EMMA_CSI0_DO
SYSTEM CONTROLLER
IC1001 (1/4)
IF_SDI
48 IM_SDI
IF_SDO
47 IM_SDO
IF_SCK
49 IM_SCK
XIF_CS
IM_CS
50
D IF_START_BIT
54 STERT_BIT
XIF_RST
68 SYSCON_REQ
EMMA_XRST
52 SYSCON_RST
EMMA_XRST BUFFER
L
IC901
DIGITAL VIDEO FORMAT CONVERTER
IC204
DT1[8] – DT1[15] HD0[10] – HD0[19]
DT1[0] – DT1[7] HD0[0] – HD0[9]
C4 DT1_HS HDMI_HS E15
B4 DT1_VS HDMI_VS E16
HDMI_CK D18
C5 DT1_CK C656DT[0] – C656DT[7]
C656HS B14
C656VS A15
C656CK B15
C656FD A16
MDT[0] – MDT[6], MAD[7],
MDT[8] – MDT[11], MAD[12],
MDT[13], MAD[14],
P17 XTAL1 MDT[15] – MDT[31]
R18 XTAL2
MAD[0] – MAD[11]
BA0, BA1
U13, U14 N4, M5
DQS[0] – DQS[3] V3, V5, V7, V9 B2, H13, H2, B13
WEZ U12
CASZ T12
RASZ T13 M2
CS1Z R13
CKE R17 N12
B12 SDA
D10 SCL CLKZ V14 M12
CLK V13 M11
A12 RESETZ
E3P_CSI0_DO
E3P_CSI0_DI
E3P_CSI0_CKO
F
GLB_XRST
E3P_CSI0_EDEN1_XCS
E3P_CSI0_EDEN2_XCS
CEC
CEC_IN 29
CEC DATA SWITCH
G
CEC_OUT 28 Q5001 – 5004
32 32
FPGA
IC401
10
10
H18 D2
H17 D1
J16 CLK3 DPCLK1 F1
8
B4
D17
A4
D18
B8
E17 DPCLK4
E16
T10
U10
DDR SD-RAM
V10
IC301
U16
DQ0 – DQ31
A0 – A7, A8(AP), A9 – A11
BA0, BA1
D9
DQS0 – DQS3
C9
L3 /WE
A9
L2 /CAS
/RAS
E7
N2 /CS
D7
CKE
D8
/CK
CK
D16
D4
C4 DEV_CLRn
X401
J3 CLK0
27MHz
DPCLK2 B5
T12 U15
U12 DPCLK7 U14
V12 V15
V13 E5
nCONFIG
J2
(Page 33)
DATA0 H7
(Page 33)
DCLK
L1
nCSO
J1
ASDO K6
AND GATE C3 INT_DONE
IC403
K17 CONF_DONE
10
GLUE_EDEN1_Y0 – 9
10
GLUE_EDEN1_C0 – 9
H (Page 33)
GLUE_EDEN1_HS
GLUE_EDEN1_VS
GLUE_EDEN1_VCK
8
GLUE_VDAC_V00 – 07
GLUE_VDAC_HS
GLUE_VDAC_VS
GLUE_VDAC_VCK
I
(Page 33)
GLUE_CSI0_DO
GLUE_CSI0_DI
GLUE_CSI0_CKO
GLUE_CSI0_XCS
10
GLUE_EDEN2_Y0 – 9
10
GLUE_EDEN2_C0 – 9
J
(Page 33)
GLUE_EDEN2_HS
GLUE_EDEN2_VS
GLUE_EDEN2_VCK
EDEN2_GLUE_HS
EDEN2_GLUE_VS (Page 33)
K
EDEN2_GLUE_VCK
CLOCK
LVDS DRIVER CONDITIONER
IC1003
IC1002
DO1+ 7 28 OSCIN
2 DI1
DO1- 8 29 OSCIN*
LVDS RECEIVER
IC1005
N+ 3 17 CLKout1
5 OUT
N- 4 18 CLKout1*
5 DATAuWire
4 CLKuWire
6 LEuWire
12 LD
INITIAL SWITCH
SW3.3V
Q401, 402
CONFIGURATION
ROM
IC402
2 DATA
6 DCLK
1 nCS
5 ASDI
SIGNAL PATH
: VIDEO