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Circuit Diagrams and PWB Layouts
Main Board: Panel Interface Sequoia
5
D
U8E
C
B
FLI32626H
A
QCG1.0S LA
10.
4
+3.3V_LVDS
C185
C186
1nF/6
0.1uF/6
+
C184
22uF/6.3V
LVDS_O_CH0+
AA18
LVDS_O_CH0P
LVDS_O_CH0-
Y18
LVDS_O_CH0N
LVDS_O_CH1+
AC18
LVDS_O_CH1P
LVDS_O_CH1-
AB18
LVDS_O_CH1N
LVDS_O_CH2+
AA17
LVDS_O_CH2P
LVDS_O_CH2-
Y17
LVDS_O_CH2N
LVDS_O_CH3+
AC17
LVDS_O_CH3P
LVDS_O_CH3-
AB17
LVDS_O_CH3N
LVDS_O_CH4+
AC16
LVDS_O_CH4P
LVDS_O_CH4-
AB16
LVDS_O_CH4N
LVDS_O_CLK+
AA16
LVDS_O_CLKP
LVDS_O_CLK-
Y16
LVDS_O_CLKN
LVDS_E_CH0+
Y15
LVDS_E_CH0P
LVDS_E_CH0-
W15
LVDS_E_CH0N
LVDS_E_CH1+
AB15
LVDS_E_CH1P
LVDS_E_CH1-
AA15
LVDS_E_CH1N
LVDS_E_CH2+
AC14
LVDS_E_CH2P
LVDS_E_CH2-
AC15
LVDS_E_CH2N
LVDS_E_CH3+
AB14
LVDS_E_CH3P
LVDS_E_CH3-
AA14
LVDS_E_CH3N
LVDS_E_CH4+
AC13
LVDS_E_CH4P
LVDS_E_CH4-
AB13
LVDS_E_CH4N
LVDS_E_CLK+
Y14
LVDS_E_CLKP
LVDS_E_CLK-
W14
LVDS_E_CLKN
PPWR
Y12
PPWR
PBIAS
W12
PBIAS
2009-Feb-20
EN 45
3
+3.3V_LVDS
LVDS_O_CH0+
LVDS_O_CH0-
LVDS_O_CH1+
LVDS_O_CH1-
LVDS_O_CH2+
LVDS_O_CH2-
LVDS_O_CH3+
LVDS_O_CH3-
LVDS_O_CH4+
LVDS_O_CH4-
LVDS_O_CLK+
LVDS_O_CLK-
LVDS_E_CH0+
LVDS_E_CH0-
LVDS_E_CH1+
LVDS_E_CH1-
LVDS_E_CH2+
LVDS_E_CH2-
LVDS_E_CH3+
LVDS_E_CH3-
LVDS_E_CH4+
LVDS_E_CH4-
LVDS_E_CLK+
LVDS_E_CLK-
PPWR
PBIAS
2
1
+3.3V_LVDS 12,19
LVDS_O_CH0+ 12
LVDS_O_CH0- 12
LVDS_O_CH1+ 12
LVDS_O_CH1- 12
LVDS_O_CH2+ 12
LVDS_O_CH2- 12
LVDS_O_CH3+ 12
LVDS_O_CH3- 12
LVDS_O_CH4+ 12
LVDS_O_CH4- 12
LVDS_O_CLK+ 12
LVDS_O_CLK- 12
LVDS_E_CH0+ 12
LVDS_E_CH0- 12
LVDS_E_CH1+ 12
LVDS_E_CH1- 12
LVDS_E_CH2+ 12
LVDS_E_CH2- 12
LVDS_E_CH3+ 12
LVDS_E_CH3- 12
LVDS_E_CH4+ 12
LVDS_E_CH4- 12
LVDS_E_CLK+ 12
LVDS_E_CLK- 12
PPWR
12
PBIAS
20
PROJECT NAME:
WLZR-A1
Title
Panel Interf_SEQUOIA
i S
e z
D
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N
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b
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A4
WLZSA1 ST FLI32626
D
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: e
Thursday, January 08, 2009
S
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18430_509_090202.eps
090202
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