Philips QCG1.0S Service Manual page 26

EN 26 8. QCG1.0S LA
8.5 Diagram Main Board: Power
Block Diagram
3
V
in
Shutdown
Pin Configuration
NAME I/O
Adj (GND) I
O
V
out
I
V
in
2009-Feb-20
IC Data Sheets
System, AP1117ELA (IC U46)
+
Thermal
PIN #
A resistor divider from this pin to the V
1
(Ground only for Fixed-Mode).
The output of the regulator. A minimum of 10uF capacitor (0.15? ? ESR ? 20? )
2
must be connected from this pin to ground to insure stability.
The input pin of regulator. Typically a large storage capacitor (0.15? ? ESR ? 20? )
is connected from this pin to ground to insure that the input voltage does not sag
3
below the minimum dropout voltage during the load transient response. This pin
must always be 1.3V higher than V
Figure 8-5 Internal block diagram and pin configuration
+
CURRENT
LIMIT
FUNCTION
out
out
+
1.25V
+
(FIXED)
pin and ground sets the output voltage
in order for the device to regulate properly.
18430_301_090204.eps
2
V
out
1
GND
Adj
1
090204