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EN 30
8.
QCG1.0S LA
8.9
Diagram
Extension Board: Audio
Block Diagram
IN1a
IN2a
SEL
IN3a
IN4a
IN1b
IN2b
SEL
IN3b
IN4b
Pin Configuration
1
IN1a
2
IN2a
3
IN3a
4
IN4a
MONa
5
NC
6
7
TONE-Ha
TONE-La
8
9
LINEa
10
OUTa
CVa
11
CVb
12
SDA
13
SCL
14
GND
15
2009-Feb-20
IC Data Sheets
input, NJW1141M (IC U24)
MONa
AGC
VOL1
AGC
VOL1
MONb
30
IN1b
29
IN2b
28
IN3b
IN4b
27
26
MONb
25
NC
24
TONE-Hb
23
TONE-Lb
22
LINEb
21
OUTb
20
AGC
19
CTH
18
CTL
17
Vref
16
16
V+
Figure 8-9 Internal block diagram and pin configuration
TONE
TONE
OUTa
-Ha
-La
TONE
VOL2
TONE
VOL2
TONE
TONE
OUTb
-Hb
-Lb
N
. o
S
y
m
b
l o
1
N I
1
a
A
c
h
n I
p
u
2
IN2a
Ach Input2
3
IN3a
Ach Input3
4
IN4a
Ach Input4
5
M
O
N
a
A
c
h
M
o
n
6
N
C
N
o
C
o
n
n
7
T
O
N
- E
H
a
A
c
h
T
e r
b
8
T
O
N
E
L -
a
A
c
h
B
a
s
9
L
N I
E
a
A
c
h
L
N I
E
1
0
O
U
T
a
A
c
h
O
u
p t
11
CVB
DAC Output for Bch Volume & Balance
12
CVA
DAC Output for Ach Volume & Balance
13
SDA
SDA Data Input (I
14
SCL
SCL Clock Input (I
1
5
G
N
D
G
N
D
T
r e
1
6
V
+
P
o
w
r e
S
u
17
Vref
Reference Voltage
18
CTL
Pop Noise reduction for Bass Control
19
CTH
Pop Noise reduction for Treble Control
2
0
A
G
C
A
G
C
F
t l i
2
1
O
U
T
b
B
c
h
O
u
p t
2
2
L
N I
E
b
B
c
h
L
N I
E
2
3
T
O
N
E
L -
b
B
c
h
B
a
s
s
2
4
T
O
N
- E
H
b
B
c
h
T
e r
b
2
5
N
C
N
o
C
o
n
n
2
6
MONb
Bch Monitor Output
2
7
IN4b
Bch Input4
2
8
N I
3
b
Bch Input3
2
9
N I
2
b
Bch Input2
3
0
N I
1
b
Bch Input1
SDA
SCL
CVA
CVB
CTH
2
I
C BUS
CTL
Interface
GND
Bias
Vcc
Vref
F
u
n
t c
o i
n
1 t
t i
r o
O
u
p t
t u
e
t c
e l
F
t l i
r e
s
F
t l i
r e
O
u
p t
t u
+ (
4
5 .
d
) B
t u
2
C
B
U
) S
2
C
B
U
) S
m
n i
l a
p
p
y l
T
r e
m
n i
l a
r e
t u
O
u
p t
t u
+ (
4
5 .
d
) B
F
t l i
r e
e l
F
t l i
r e
e
t c
18430_307_090204.eps
090204
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