Yamaha CD-S2100 Service Manual page 45

Pin
Port Name
No.
41 P5_5/nHOLD
42 P5_4/nHLDA
43 P5_3/BCLK
44 P5_2/nRD
45 P5_1/nWRH/nBHE
46 P5_0/nWRL/nWR
47 P4_7/PWM1/TXD7/SDA7/nCS3 FPGA_INITN
48 P4_6/PWM0/RXD7/SCL7/nCS2 FPGA_DONE
49 P4_5/CLK7/nCS1
50 P4_4/nCTS7/nRTS7/nCS0
51 P4_3/A19
52 P4_2/A18
53 P4_1/A17
54 P4_0/A16
55 P3_7/A15
56 P3_6/A14
57 P3_5/A13
58 P3_4/A12
59 P3_3/A11
60 P3_2/A10
61 P3_1/A9
62 Vcc2
63 P3_0/A8
64 Vss
65 P2_7/AN2_7/A7
66 P2_6/AN2_6/A6
67 P2_5/INT7/AN2_5/A5
68 P2_4/INT6/AN2_4/A4
69 P2_3/AN2_3/A3
70 P2_2/AN2_2/A2
71 P2_1/AN2_1/A1
72 P2_0/AN2_0/A0
73 P1_7/nINT5/IDU/D15
74 P1_6/nINT4/IDW/D14
75 P1_5/INT3/IDV/D13
76 P1_4/D12
I/O
Function Name
(P.C.B.)
STBY_CNT/N_EMP I, O O
TRAY_MTR2 O O
TRAY_MTR1 O O
CLAMP_MTR2 O O
CLAMP_MTR1 O O
UNCLAMP_SW/N_CE I O
I O
I O
FPGA_PROG O O
CLAMP_SW I O
FPGA_SELC O O
FPGA_SELB O O
FPGA_SELA I O
SSP2_YOSI_MUTE I O
SSP2_N_DSPSTOP I O
SSP2_DSD_PCM I O
SSP2_YISO_MUTE I O
SSP2_USB_RDY I O
SSP2_N_IC O O
SSP2_PON O O
LED_PWR O O
VCC2 MCU MCU
FPGA_RRESET O O
VSS All MCU
DPWR_ON O O
PWR_RY O O
ACPWR_DET IRQ O
CD_PWR_DET I O
SW_CD_OTHER O O
FPGA_JTAGEN O O
CD_RST O O
FPGA_IO2 O O
DIR_N_INT IRQ O
CD_MUTE I O
CD_SPDIF_RQ O O
CD_PWR O O
O For flash writing (IO)
BOOT mode: P5_5=L, CNVSS=H, P5_0=H
Set to Pull-down as Hiz state may occur during emulator operation.
• +5SPC power ONOFF control
(L=OFF, H=ON: For reduction of stand-by power)
• Usually fixed at Low standby power is reduced (MCUSleep) by
setting to Low after processing required for standby state.
When shifting to the stand-by state, set to Low after completion
procedure
O Tray motor control
O Tray motor control
O Clamper control
O Clamper control
O For flash writing (HI)
BOOT mode: P5-5=L, CNVSS=H, P5_0=H / Clamper detection
O Readiness for FPGA/GPLD configuration is indicated
PU is enabled during configuration in FPGA
O FPGA Config DONE input
Completion of configuration sequence and starting sequence
going on are indicated
O FPGA Config starting / Configuration started at L
Note: Do not apply trigger to the device when DONE is at Low
O Clamper detection
O FPGA sound output selection / Designated with 3 bit
O FPGA sound output selection / Designated with 3 bit
O FPGA sound output selection / Designated with 3 bit
O USB streaming controller TE8802 control / Output resolutions
0: 16bit, 1: 24bit
O USB streaming controller SSP2 control
DSP function unavailable
O USB streaming controller SSP2 control
DSD/PCM status input from driver via SSP2
O USB streaming controller SSP2 control
MUTE request input due to SSP2 error
O USB streaming controller SSP2 control / USB ready state input
Whether USB available or not is judged
O USB streaming controller SSP2 control IC output
O USB streaming controller power control for SSP2 control
High=On, Low=Off
O LED_POWER control / H: On, L: Off
MCU +5M
O FPGA / Register reset
D_GND
O Power for digital 33D, 15D 115D, VBUS On/Off
High: On, Low: Off
O Power relay control
O AC power input detection
O Vaddis886 SDRAM CLOCK enable control monitor
O For switching control between CD and other functions
CD=H, Other=L
O FPGA
L=TDI, TDO, TMS, TCK functions as general purpose I/O
H=TDI, TDO, TMS, TCK functions as JTAG pin
O SA-CD MODULE control reset output
O Communication between CPLDs serial data
O DIR DIX9210 control interrupt input
O SA-CD MODULE MUTE detection
O SA-CD MODULE (Vaddis886) control SPDIF request output
O SA-CD MODULE control power On/Off control
High: On, Low: Off
CD-S2100
Detail of Function
45