Sony SCD-XA777ES Service Manual page 77

Pin No. Pin Name
45 AVSS0
46 IGEN
47 AVDD0
48 ASYO
49 ASYI
50 RFAC
51 AVSS1
52 CLTV
53 FILO
54 FILI
55 PCO
56 AVDD1
57 BIAS
58 VCTL
59 V16M
60 VPCO
61 DVDD2
62 ASYE
63 MD2
64 DOUT
65 LRCK
66 PCMD
67 BCLK
68 EMPH
69 XTSL
70 DVSS2
71 XTAI
72 XTAO
73 SOUT
74 SOCK
75 XOLT
76 SQSO
77 SQCK
78 SCOR
79 SBSO
80 EXCK
I/O
—
Ground terminal (analog system)
I Stabilized current input for operational amplifiers
—
Power supply terminal (+3.3V) (analog system)
O
Playback EFM full-swing output terminal
I
Playback EFM asymmetry comparator voltage input terminal
I EFM RF signal (AC level) input from the CXD1881R (IC001)
—
Ground terminal (analog system)
I
Internal VCO control voltage input of the EFM playback master PLL
O
Filter output for master clock of the playback EFM master PLL
I Filter input for master clock of the playback EFM master PLL
O
Phase comparison output for master clock of the playback EFM master PLL
—
Power supply terminal (+3.3V) (analog system)
I
Playback EFM asymmetry circuit constant current input terminal
I Control voltage input terminal for the variable pitch Not used (fixed at "L")
O
16.9344 MHz clock signal output Not used (open)
O
PLL charge pump output terminal for the variable pitch Not used (fixed at "L")
—
Power supply terminal (+3.3V) (digital system)
Playback EFM asymmetry circuit on/off selection signal input terminal
I
Not used (fixed at "H")
Digital out on/off control signal input from the CPU (IC901)
I
"L": digital out on, "H": digital out off
O
Digital audio signal output to the DIGITAL (CD) OUT OPTICAL (IC442)
L/R sampling clock signal (44.1 kHz) output to the digital filter (IC101, 201, 1101, 1201, 2101,
O
2201), SACD decoder (IC701), and CXD9647R (IC803)
Serial data output to the digital filter (IC101, 201, 1101, 1201, 2101, 2201), SACD decoder
O
(IC701), and CXD9647R (IC803)
Bit clock signal (2.8224 MHz) output to the digital filter (IC101, 201, 1101, 1201, 2101, 2201),
O
SACD decoder (IC701), and CXD9647R (IC803)
O
Playback disc output terminal in emphasis mode Not used (open)
I Input terminal for the system clock frequency setting
—
Ground terminal (digital system)
I
System clock input terminal (33.86688 MHz)
O
System clock output terminal (33.86688 MHz) Not used (open)
O Not used (open)
O
Not used (open)
I
Not used (open)
O
Subcode Q data output to the CPU (IC901)
I Subcode Q data reading clock signal input from the CPU (IC901)
O
Not used (open)
O
Subcode serial data output to the SACD decoder (IC701)
I
Subcode serial data reading clock signal input to the SACD decoder (IC701)
Description
Fixed at "H" in this set
SCD-XA777ES
77