Integra DTR-7.7 Service Manual page 78

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -10
Q285: IC42S16100 (16-Mbit Synchronous Dynamic RAM)
BLOCK DIAGRAM
CLK
CKE
COMMAND
CS
DECODER
RAS
&
CAS
CLOCK
WE
GENERATOR
A11 1
A10
A9
REFRESH
A8 CONTROLLER
A7
A6
REFRESH
A5
COUNTER
A4
A3
A2
A1
A0
ROW
ADDRESS
LATCH
11
PIN CONFIGURATION
ROW
ADDRESS
BUFFER
MODE
11
REGISTER
11
8
SELF
REFRESH
CONTROLLER
ROW
ADDRESS
BUFFER
11
VCC 1
I/O0 2
I/O1 3
GNDQ 4
I/O2 5
I/O3 6
VCCQ 7
I/O4 8
I/O5 9
GNDQ 10
I/O6 11
I/O7 12
VCCQ 13
LDQM 14
WE 15
CAS 16
RAS 17
CS 18
A11 19
A10 20
A0 21
A1 22
A2 23
A3 24
VCC 25
MEMORY CELL
ARRAY
2048
BANK 0
11
SENSE AMP I/O GATE
256
COLUMN DECODER
8
256
SENSE AMP I/O GATE
MEMORY CELL
ARRAY
2048
BANK 1
11
50 GND
49 I/O15
48 I/O14
47 GNDQ
46 I/O13
45 I/O12
44 VCCQ
43 I/O11
42 I/O10
41 GNDQ
40 I/O9
39 I/O8
38 VCCQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 GND
DTR-7.7
DQM
DATA IN
BUFFER
16 16
I/O 0-15
DATA OUT
BUFFER
16 16
Vcc/VccQ
GND/GNDQ