Display Data Channel Circuit; Ddc1; Ddc2B And Ddc2Ab - Sony CPD-420GS Training Manual

Display Data Channel Circuit

DDC1

The front input supports DDC1 communications. The front input cable pin
12 (SDA) and pin 15 (SCL) are connected to CN312 pin 1 (DDCSCL) and
pin 2 (DDCSDA) on the A Board. IC007 EEPROM pin 5 (SDA) and pin 6
(SCL) provides the host with DDC1 communication. The V Sync input to
IC007/7 (VCLK) is used to synchronize the timing of the data reading
cycle.
IC007/7 VCLK
55

DDC2B and DDC2AB

The rear input supports DDC2B and DDC2AB communications. The rear
input cable pin 12 (SDA) and pin 15 (SCL) are connected to CN310 pin 2
(DDCSCL) and pin 3 (DDCSDA) on the A Board. The data is passed
through the A Board to CN311 pin 2 (DDCSCL) and pin 3 (DDCSDA).
CN311 is connected to the N Board via connector CN1003 pin 2 (DDCCLK)
and pin 3 (DDCDATA) and are input to IC1001 pin 34 (DDCCLK) and pin
35 (DDCDATA).
CN311/3 DDCSDA