Domino (Dmn-8602) - Samsung BD-P1000 Service Manual

Circuit Operating Descriptions

13-5 Domino (DMN-8602)

SPARC Processor Core
I-Cache
Audio DSP
and
Memory
1x8/1x10 YUV
Video
1x8
Interface
YUV
2Port
Audio
Interface
S/PDIF
4- 4-
Port Port
1) SPARC Processors
Two 32-bit SPARC processors, one dedicated to video processing and the other assigned general system tasks
and audio processing, performthree classes of functions: system processing, audio processing, and high-level
control flow and decision-making tasks for video processing.
Optionally, they can also perform 2D graphics and host functions.
The SPARC processors have a programmable, scalable architecture that includes an internal 16 Kbyte
instruction cache and an internal configurable 16 Kbyte data memory/cache. Data memory is used instead
of a data cache when the software needs predictable real-time performance and overlapped DMA transfers.
Each SPARC delivers 150 MIPS of processing power.
The DMN-8602 device integrates a 2D graphics accelerator on the dual SPARC processors.
This graphics accelerator supports:
◆ On-Screen Display (OSD)
◆ 2D graphical user interfaces
◆ A 32-bit RGBA with an 8-bit alpha blending channel, flicker filters, and a high-quality video scaler.
The DMN-8602 also supports multiple video inputs, windowed video and graphics with arbitrarily
relocatable and resizable windows, PiP (Picturein-Picture), letterbox, and side-by-side display of SD sources.
2) Memory Mapping
The following paragraphs and figures summarize the DMN-8602 memory map for different configurations.
These configurations include SDRAM access and access to internal registers via the internal Control Bus
(CBus).
13-8
SPARC Processor Core
Data
I-Cache
Memory/
Cache
Host Audio DSP
and and
Graphics Memory
Video DSP
and
Memory
64
Bitstream/
Host
Storage
Interface
Interface
16/32
Data
Memory/
Cache
Host
SDRAM
and
SGRAM
Graphics
Array
32
Motion
Memory
Estimator
Controller
and Memory
1394
USB
Link
Interface
Interface
Fig. 13-7
Serial I/O DENC
Samsung Electronics