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1. Description
1.3 Principle of operation
Interface module
6ES5772-OAA12
G e n e r a l :
The 6ES5772-OAA12 modules enable up to 15 individual S5-010
The master PC must have eiaht inputs and 13 outputs for 24 V. The
programmable controllers to be interfaced to a higher-ranking PC
peripheral bus carries the fdlowing signals:
(e.g. S5-150), one such module being needed for each PC. This
arrangement is particularly meaningful when the PCs of several
- 8 bits for 8 binary signals from the SS-010 W PC
autonomous individual machines of, for example, a production line
(inputs of the master PC)
are t o oaerate under a hiaher-rankina control svstem.
- 8 bits for 8 binary signals to the S5-010 W PC
v
(outputs of the master PC)
Signal interchange takes place on a peripheral bus which is looped
- 4 bits for addressing the interface modules
through all the interface modules, starting from the master PC.
- 1 bit for lowlhigh byte selection
It should be pointed out that a radial arrangement of the peripheral
In addition to these 21 signal lines a further two are needed for the
bus is possible and may be the better solution for many applica-
24 V supply so that a 24-core SlMATlC cable can be used.
tions. It avoids, for example, having to shut down all the S5-010
PCs when changing modules in only one of them.
Fig.
10 Interfacing up to 15 55-010 Wprogrammable controllers t o a master PC
PC
2
PC;
3
No
of E s
5
15
All inputs and outputs, including the address bits, are galvanically
The outputs have an output load capability of 30 mA and are
isolated from the S5-010 PCs, which means that the individual PCs
current-limited. Since the peripheral bus runs through n
d
15 inter-
can have different reference potentials. The +24 Vand M (reference
face modules, all the eight outputs of an interface module are
potential) connections to the interface module must be taken from
connected in parallel with n
-
1 outputs of the other interface
the power source supplying the inputloutput modules of the master
modules. The mutual loading of the outputs due to the paralleling is
PC.
n
X
1 mA. The load capability of each output is reduced by this
amount.
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