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3-77.
Switch
selections are
made
through
switch dnvers
which
rely
on Vcc
and
Vss being
at
-l.SV
and
—20V
with
respect to analog
common.
This
allows simple
Iransi-
liori
from
TTL
levels
to
FET
off
voltages.
D/A
Converter
switches
are selected
on
transition
of
U3l from
one
state
to
the next.
The
transition
clocks
the
first
of
two
"D"
flip-flops
which
sets
the
second.
The
output of
the
second
larch resets
the
first
and
selects
the switch.
If
the
polarity
does not change
after
closing
a
switch, the
output of
U6
plus
the
output
of
Ull
(reference
select)
will
place
two
highs
on
the
input
of one
section
of
AND
gate
U25.
Through
OR
gate,U16,
a
one
will
be
applied to
the
D
input
of
that
switch
latch.
The
next
transition
of
U31
will
clock
the hitch,
keeping
the switch
closed. If
the
polarity
had
changed,
a
zero
would
be
applied to the
D
input,
opening
the switch.
3-78.
After the
last
step,
at
completion of
a
sample,
the Controller addresses the
A/D
Converter
for
autozero.
U3
1
is
clocked to the
C7
state
causing a
digital reset.
When
U6,
storage
capacitor
disable,
is
reset,
autozero
is
enabled.
RC
coupled
gates
delay
the zero switch controls so that
switch
A1
may
be
closed
and
A2
opened
in
the reference
switching
circuit.
This provides
a
faster settling
time
for
the
reference switching amplifier.
Both
A1 and
A2
are
opened
during the
autozero
time.
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