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8502A
INI
A
remove
the wait
state
Umiting
the
wait time
to a
single
machine
state.
3-47.
ACK
LOGIC
348,
When
a
module
is
addressed
by
the Controller,
or
enabled
for interrupt identification
by
INA
from
the
Con-
troller,
it
must
return an
ACK
(high)
signal.
Refer
to
Figure
3-13. Either
INTA
(for interrupts)
or
Ai5
(for external
addr
esses)
t
ogether
w
ith
the de
layed
ACK
signal
produce
DLD ACK
for
U38.
OLD ACK
resets
the
ACK
interrupt
logic,
which
is
timing
the wait
for
ACK,
and produces
the
ACK
LAT
signal througli
UI5
and U27.
RRDY
must
be
low
to
get
ACK
LAT.
This synchronizes
ACK LAT
to the
SYNC rrL
signal.
ACK LAT
(or
ACK
!NT
TIL
if
an
ACK
is
missing) causes the microprocessor
to exit
the wait
state.
349.
INTERUPTS
3-50.
Two
internal interrupts
and
four
possible external
interrupts
are
applied to the
interrupt
(INT)
control
logic
(Figure 3-13).
A
low on
OR
gate
U17
places
a
high
on
NAND
gate
U38.
When INTE
is
high
from
the microproces-
sor
(during the
last
state
of an
Instruction cycle),
U38
out-
puts
a
low
through an
RC
delay
network
to
U32.
U32
inverts the signal
and
places
a
high
on
the
INT
line
to inter-
rupt the
microprocessor.
The
microprocessor drops
INTE
low, then puts
out an
interrupt
acknowledge
(INTA)
as
a
status
word which
is
latched
up
in
the
Status Latch,
U18.
Then
the
microprocessor
enters
a
wait
state until
the
inter-
rupt
and
its
priority are identified
through
INT
VECTOR,
U28
(Controller
scheriiatic,
Section
8).
3-.S1.
Interna! interrupts are
ACK
INT
and
MARK
INT
(Figure
3-14).
ACK
INT
logic consists
of
a
retriggerable
FROM
data
bus
CONTROL
iINT
DBO
DB1
DB4
DB7
Figure
3-11.
Status Latch
ACK
INT
TTL (FROM
ACK
INT LOGIC!
A15
+
INTA (FROM
ACK
LOGIC)
ACK LAT
(FROM
ACK
LOGIC)
•SYN
IINT
(FROM STATUS
LATCH)
•INTA
(FROM STATUS
LATCH)
INTE (FROMjUP)
INT
(FROM
INT
CONTROL)
A15
TTL
(FROM/iP)
SYNC TTL
(FROM
MP)
3-10
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