Hitachi DV-P345E Service Manual page 6

DACTEST[6] I
VID[5] // O //
ICETDO // O //
130 DJTDO // O //
IDGPCI/O[1]// I/O //
DACTEST[5] I
VID[4] // O //
ICETCK // I //
131 DJTCK // I //
GPCI/O[27]// I/O //
DACTEST[4] I
VID[3] // O //
DJTMS // I //
132 GPCI/O[28]// I/O //
DACTEST[3] // I //
SERVOCLK O
VID[2] // O //
DJTDI // I //
133 GPCI/O[29]// I/O //
DACTEST[2] // I //
SSEL[0] O
VID[1] // O //
DJTDO // O //
134 GPCI/O[30]// I/O //
DACTEST[1] // I //
SSEL[1] O
VID[0] // O //
DJTCK // I //
135 ICGPCI/O[3]// I/O //
DACTEST[0] // I //
SSEL[2] O
VCLKx2 // O //
COSYNC // O //
ICGPCI/O[1]// I/O //
DACs test input
Digital video luma/chroma output, multiplexed in time according to the
CCIR656 standard (for interlaced video) or luma (for progressive) //
ADP debug interface //
DSP debug interface //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW. When input, the pin can be used as general purpose external interrupt
to the DSP//
DACs test input
Digital video luma/chroma output, multiplexed in time according to the
CCIR656 standard (for interlaced video) or luma (for progressive) //
ADP debug interface /
DSP debug interface //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW //
DACs test input
Digital video luma/chroma output, multiplexed in time according to the
CCIR656 standard (for interlaced video) or luma (for progressive) //
DSP debug interface //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW //
DACs test input //
SERVO channel clock output for AFE by-pass
Digital video luma/chroma output, multiplexed in time according to the
CCIR656 standard (for interlaced video) or luma (for progressive) //
DSP debug interface //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW //
DACs test input //
SERVO channel select output for AFE by-pass
Digital video luma/chroma output, multiplexed in time according to the
CCIR656 standard (for interlaced video) or luma (for progressive) //
DSP debug interface //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW //
DACs test input //
SERVO channel select output for AFE by-pass
Digital video luma/chroma output, multiplexed in time according to the
CCIR656 standard (for interlaced video) or luma (for progressive) //
DSP debug interface //
General purpose input/output pin, monitored/controlled by the CPU or DSP
SW. When input, the pin can be used as general purpose external interrupt
to the CPU //
DACs test input //
SERVO channel select output for AFE by-pass
Digital video clock output. 27.000MHz //
Composite sync output. Active only when component analog output is
selected //
General purpose input/output pin, monitored/controlled by the CPU or DSP
6
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