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No. 1 Pin name / I/O /
Connection
Function
XV-Cl
ou
43
(DGND
1 -
1 Power.
( High-voltage
power ground (OV).
44
/DY
I
I
0
Output to TFT panel.
r TFT panel's Y-direction shift data output (VDD2 line).
45
CLY
46
CLY
0
Output to TFT panel.
TFT panel's Y-direction transfer clock output (VDD2 line).
0
Output to TFT panel.
TFT panel's Y-direction transfer clock output (VDD2 line).
47
ENOUT
0
Output to TFT panel.
TFT panel's enable signal output (VDD2 line).
48
(VDD2
1 -
( Power.
High-voltage
power 2 (+I 2.OV typical).
49jDGND
j
-
j Power.
High-voltage
ground (OV).
50ITEST6
(
I
(
Test terminal input.
51
OE
I
52
NAOUT
0
Output enable control input.
NAND output.
53lNAlNP
j
I
/
NAND input 2.
54/NAINl
l I l .
I
NAND input 1.
55
RGBINV
0
56
FRP
0
IV inverted signal output (output to chroma IC).
1 H inverted signal output (output to chroma IC).
57
CSYNC
I
Composite sync signal input.
58
IMVSYNC
1 0
(
Vertical sync signal monitor output.
59
VLS
0
Output to video circuit.
Video level setting signal output for WIDE mode.
60
INVIN2
I
Inverter input 2.
61
INVOUT2
0
Inverter output 2.
62
MFS
0
Field ID signal monitor output.
63
VCC
-
Power.
Logic circuit power (+5V typical).
64
GND
-
Power.
Logic circuit power ground (OV).
The GND and DGND pins are interconnected
inside the chip with a resistor in between.
Be sure to keep
both pins at the same potential.
When the OE input level gets low, all the output signals to the TFT panel - DX, CLXi, CLXi (i =l thru 4),
DY, CLY, CLY, and ENOUT - come to low level too.
Be sure to fix the non-used inverter input and NAND input at the high or low level.
Switching
between the VIDEO and WIDE modes goes as follows depending
on the WMODE and
VMODE input levels.
L: Low level, H: High level.
.
WMODE
VMODE
Display mode
Remarks
L
L
NTSC
-
L
H
Intermittent
PAL
-
H
H
Letter box (NTSC)
VLS:
During the "H" period, the black-level video
signal is put into the TFT panel.
In the power-saving
mode with no display, the CLXl thru CLX4 signals are all at low level, whereas the
CLX1 thru CLX4 signals all at high level.
Keep all the test terminal inputs at low level.
'
Keep open the test terminal reference signal outputs - MOUTl
and MOUT2.
41
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