Asus A7V333 Manual page 2

magnification, that is, you can artificially blow up a few things but the raw performance does not really change too much.
One possible and very clean way out of this dilemma would have been to increase the FSB from the current 133 MHz to the next
level, that is 166 MHz, along with offering the option of running the memory at Host Clock or -PCI frequency as precedented by VIA's
earlier P2/PIII chipsets and get on with business as usual. Needless to say that this development was part of the original Athlon
roadmap showing FSB frequencies of up to 200 / 400 MHz clock / data rate. As so often, however, Thor, the chief of the Norse Gods
in Walhalla threw his Hammer to disrupt the activities of the earthlings. Well, just substitute Dresden for Walhalla, Hammer still
remains Hammer and the net effect is the same as long as you accept Athlons as Earthlings.
Bottomline is that Hammer appears to come along faster than anticipated, allowing AMD to skip some of their planned stepping
stones on the roadmap from Athlon to Hammer. The latest victim is Barton's new clothes in form of SOI, other casualties are the
higher FSB versions, that is 166 or 200 MHz. Basically, the reason is nothing but the fact that going through the tedious process of
validating every last bit of functionality is not worth the effort in view of an entirely new platform already knocking at the door.
Heart of the new and improved VIA KT333A chipset is the KT333 NorthBridge (CD or higher reviwion)
On the other end of the seesaw, VIA Technologies have been spinning their own agenda, that is, shooting for being the number one
performance chipset supplier for the Socket A platform and they have done an extraordinarily good job. Granted that there are some
errata or insufficiencies in the IDE transfer as reported elsewhere but there are also some simple workarounds in the form of
increasing the PCI latency as long as the BIOS interface supports this option or else using the patch provided by George Breese to
change the PCI registers on the fly and accomplish the same net effect.
Still, the DRAM industry has been running off with performance of DDR ever since the introduction of the platform and why not use
the existing FSB scheme with a higher memory bus as done earlier with the Apollo and KX chipset series. In other words, there is a
new niche in the chipset market and there are new chipsets to fill it. The first revisions a.k.a. KT333 (chip markings lower than "CD")
were immediately replaced with the KT333A (chip markings CD and higher) and there are already a number of mainboards available
sporting the newest core logic revision.
We will have more on the different boards in the coming weeks, for now, we are going to start with the ASUS A7V333
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