Asus A7V333 Manual page 19

LOSTCIRCUITS
ASUS A7V333
Hit me with the voltage regulators ..
(Review by MS, April 24, 2002)
Performance
Memory Subsystem / SiSoft Sandra 2002
As already mentioned, running the memory bus at 166MHz or at 5:4 harmonics of the external CPU bus requires some mechanisms
to translate the higher memory speed to the same data rate at which the EV6 bus is running. These mechanisms include serially
connected buffers that accept the data on one end and spit them out at the other side. Suffice it to say that each buffer stage requires
an extra clock cycle until the data are forwarded, in other words, the extra latencies eat up a substantial amount of bandwidth.
Exacerbating is that, since the CPU bus runs at 266 Mbsp (Megabit/ sec and pin) and 64 bit width, there is an a priori limitation to
2100 MB/s between CPU and chipset that cannot be exceeded.
Buffering Enabled
Buffering Enabled essentially means that prefetching is allowed and the memory bus is operating under optimized, streaming
conditions that are limited mostly by the page size and Page Hit limitations (if those are imposed by the controller). With an optimized
path, current high-end systems are capable of achieving up to roughly 95% bus utilization. That is, with a PC2100 interface,
bandwidth rates of 2050 are not uncommon. The big question is, how the asynchronous memory bus behaves under these
conditions, especially since, as mentioned above, the CPU bus cannot handle more than 2100 MB/sec in the first place.
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At One Glance
Features
Layout Ln-board
Peripherals
Jump, Jumper,
Jumperst
Dip Switch, Connectors
BIOS, Test
Configuration
SiSoft Sandra
Content Creation
WS2001, Expendable
Quake3 Arena, 3DMark
Overclocking,
Conclusion
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