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6-3. Explanation of functions
o Basic configuration of filter
This LSI makes it possible to 4-fold oversampling
out-
put of both L and R channels from a single chip' When the
sampling frequency of the input is 44'1kHz, the output
rate
i s 1 7 6 . 4 k H 2 .
This LSI incorporates two stages of linear-phase
FIR
(non-cyclic) filters connected in series' The 1st stage output
i s t h e 2 - f o l d o v e r s a m p l i n g o u t p u t , a n d t h e 2 n d s t a g e o u t p u t
is the 4-fold oversampling output'
CIRCUIT DESCRIPTION
Fig.6-2
F i g . 7 - 1
Fig. 6-2 shows the simplified diagram of filter configu-
ration. The lst stage filter (DFl) is an 8O-step FIR type
filter, and.the 2nd stage filter (DF2) is a 15-step FIR type
filter. Both filters have the.2-fold oversampling function,
so that a total of 4-fold oversampling output can be ob-
t a i n e d .
OUTPUT
176.4kH2
(4-fold over-
sampling)
7. Signal processor lC: CX23035 (X32-1090-11 : lC3)
7-1. Block diagram
E g s
9 9 I
; N F
I' s
-
t
=
o
a a
o
6
t 0 0 3 u u '
l S U E u o o
e
o
9
3 8 3 ,
ERROR DET.
€RROR CORRECTION
EEEHa R HgFHsBEEaE
1 4
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