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C I R C U I T D E S C R I P T I O N
2-2. Distortion correction circuit (X25-2860-11)
I n F i g . 2 - 2 , D - F F 1 , D - F F 2 , B C 1 a n d B C 2 f o r m t h e
circuit which extracts the data logic of the digital audio
d a t a ' s 1 s t h b i t w h i c h i s i m m e d i a t e l y a f t e r t h e M S B , a n d
delays the logic by DATA. For the details of the opera-
t i o n , p l e a s e r e f e r t o t h e t i m i n g c h a r t i n F i g . 2 - 3 .
The DAC has been designed to accept the connection
of the circuit which compensates for the error of the cur-
rent value corresponding to the value of the MSB. The
circuit consists of semi-fixed resistor VR1 and resistors R1
t o R 3 .
OP1 is used to add/subtract the current compensating
t h e e r r o r c o r r e s p o n d i n g t o t h e v a l u e o f t h e 1 5 t h O i t t o /
from the D/A converted current. Therefore, when the
current corresponding to the 1 sth bit is output from the
DAC according to the logic of the 15th bit, the current
passes through OPi so that the error corresponding to the
v a l u e o f t h e 1 s t h b i t i s e l i m i n a t e d . l f t h e c u r r e n t c o r r e s -
p o n d i n g t o t h e 1 s t h b i t i s n o t o u t p u t f r o m t h e D A C , t h e
Fig. 2-2 Distortion correction circuit
output from OP1 becomes 0V, so that the compensation
current is not applied to the D/A converted current output
f r o m t h e D A C .
C L K
4.2336
M H z
DATA
LATCH
176.4kH2
(n-1)th DATA
{n)th DATA
C
D A T A 1 5 l o s i c [ ( n - 1 ] t h l
D A T A 1 5 l o g i c [ ( n + 1 ) t h ]
D
X
D A T A 1 s l o s i c t ( n - 1 ) t h l
X
D A T A 1 5 t o s i c [ ( n ] t h l
I
\
Fig. 2-3 Timing chart of distortion coruection circuit
2-3. Dropout controller circuit (X29-1780-00)
With conventional servo systems, tracking error signal
T E f r o m p i n 1 7 T E o f C X 2 O ' I 8 9 a r e o u t p u t d i r e c t l y a t p i n
i of CN3. However, with the DP-3300D, the waveform of
TE is shaped, the shape of waveform TE varies while it
passes through lC3. The operations and waveforms in this
process are as follows.
D A T A 1 5 l o g i c [ ( n + 1 ) t h ]
n;r fE
r c g l f
@
IE
Fig. 2-4 Dropout controller circuit
1 0
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