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VMIC VMICPCI-7715 Product Manual

Single board, all rear i/o pentium iii socket 370 processor-based compactpci sbc
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VMICPCI-7715
®
Single Board, All Rear I/O Pentium III
Socket 370
Processor-Based CompactPCI SBC
Product Manual
12090 South Memorial Parkway
Huntsville, Alabama 35803-3308, USA
500-657715-000 Rev. A
(256) 880-0444
(800) 322-3616
Fax: (256) 882-0859

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  • Page 1 VMICPCI-7715 ® Single Board, All Rear I/O Pentium III Socket 370 Processor-Based CompactPCI SBC Product Manual 12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA 500-657715-000 Rev. A (256) 880-0444 (800) 322-3616 Fax: (256) 882-0859...
  • Page 3 VMIC reserves the right to make any changes, without notice, to this or any of VMIC’s products to improve reliability, performance, function, or design. VMIC does not assume any liability arising out of the application or use of any product or circuit described herein; nor does VMIC convey any license under its patent rights or the rights of others.

  • Page 5: Table Of Contents

    VMICPCI-7715 Product Options ........
  • Page 6 Ethernet Controller ............... . . 10BaseT .
  • Page 7 Appendix B - System Driver Software ..........Driver Software Installation .
  • Page 8 Large Disk Access Mode ............. . . Local Bus IDE Adapter .
  • Page 9 Appendix F - Sample C Software ............Directory CPU .
  • Page 11 VMICPCI-7715 Board Jumper Locations ........
  • Page 13 Table 3-1 VMICPCI-7715, Interface Memory Address Map ....... . .
  • Page 14 Table 4-12 Status Byte Description ............Table 4-13 LOAD Bit Operation .

  • Page 15: Overview

    PC/AT-compatible operating system. The PC/AT mode of the VMICPCI-7715 is discussed in Chapter 3 of this manual. The VMICPCI-7715 also operates as a CPCI system slot SBC and interacts with other CPCI modules via the on-board embedded bridge. The VMICPCI-7715 also provides capabilities beyond the features of a typical PC/AT compatible CPU, including a programmable Watchdog Timer, nonvolatile SRAM, Independent 16 Bit Timers and a bootable DiskOnChip system.

  • Page 16: Organization Of The Manual

    VMICPCI-7612 Product Manual Organization of the Manual This manual is composed of the following chapters and appendices: Chapter 1 - VMICPCI-7715 Features and Options describes the features of the base unit. Chapter 2 - Installation and Setup describes unpacking, inspection, hardware jumper settings, connector definitions, installation, system setup and operation of the VMICPCI-7715.

  • Page 17: References

    References References Some reference sources helpful in using or programming the VMICPCI-7715 include: Pentium III Processors and Related Products Intel Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641 (800) 548-4752 www.intel.com Intel 440BX PCIset 82443BX PCI and Memory Controller (PMC) 82443BX Data Bus Accelerator (DBX)
  • Page 18 VMICPCI-7612 Product Manual For additional information please refer to the following Intel 82440BX AGP set: 82443BX Host Bridge/Controller Intel Corporation 2200 Mission College Blvd. P.O. Box 58119 Santa Clara, CA 95052-8119 Intel 82440BX PCIset ISA Bridge 82371EB PCI ISA IDE Xcellerator (PIIX4E) 2200 Mission College Blvd.
  • Page 19 References Intel 69030AGP Video Controller Intel Corporation P.O. Box 58119 Santa Clara, CA 95052-8119 (408) 765-8080 www.intel.com Phillips PCA9540 Smbus Multiplexer Phillips Semiconductors 811 East Arques Ave. P.O. Box 3409 Sunnyvale, CA 94088-3409 1-800-234-7381 www.semiconductors.phillips.com CMC Specification, P1386/Draft 2.0 from: IEEE Standards Department Copyrights and Permissions 445 Hoes Lanes, P.O.

  • Page 20: Safety Summary

    Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture and intended use of this product. VMIC assumes no liability for the customer’s failure to comply with these requirements. Ground the System To minimize shock hazard, the chassis and system cabinet must be connected to an electrical ground.

  • Page 21: Safety Symbols Used In This Manual

    Safety Symbols Used In This Manual Safety Symbols Used In This Manual Indicates dangerous voltage (terminals fed from the interior by voltage exceeding 1000 V are so marked). Protective conductor terminal. For protection against electrical shock in case of a fault. Used with field wiring terminals to indicate the terminal which must be connected to ground before operating equipment.
  • Page 22 VMICPCI-7612 Product Manual...

  • Page 23: Chapter 1 - Vmicpci-7715 Features And Options

    CompactPCI Features ..........26 Introduction The VMICPCI-7715 performs all the functions of a standard IBM PC/AT motherboard with the following features: •...

  • Page 24: Table 1-1

    VMICPCI-7715 Product Manual The VMICPCI-7715 supports standard PC/AT I/O features such as those listed in Table 1-1. Figure 1-1 on page 25 shows a block diagram of the VMICPCI-7715 emphasizing the I/O features. Table 1-1 PC/AT I/O Features I/O FEATURE...

  • Page 25: Figure 1-1 Vmicpci-7715 Block Diagram

    EIDE Philips PCA9540 Hard COM Port 1 Drive DiskOnChip COM Port 2 Socket Optional SUPER 16 Bit Timers with 82C54 Flash BIOS Watchdog Timer Floppy Drive DS1384 FDC37C67X Non Volatile SRAM PS/2 Keyboard / Mouse Figure 1-1 VMICPCI-7715 Block Diagram...

  • Page 26: Compactpci Features

    These configurations involve processor performance, the DiskOnChip, and SDRAM memory size. These options are subject to change based on emerging technologies and availability of vendor configurations. The options and current details available with the VMICPCI-7715 are defined in the device specification sheet available from your VMIC representative.
  • Page 27 CompactPCI Features...
  • Page 28 VMICPCI-7715 Product Manual...

  • Page 29: Chapter 2 - Installation And Setup

    All claims arising from shipping damage should be filed with the carrier and a complete report sent to VMIC Customer Service along with a request for advice concerning the disposition of the damaged item(s).

  • Page 30: Hardware Setup

    VMICPCI-7715 Product Manual Hardware Setup The VMICPCI-7715 is factory populated with user-specified options as part of the VMICPCI-7715 ordering information. The CPU speed, SDRAM and DiskOnChip size are not user-upgradable. To change these options, contact customer service to receive a Return Material Authorization (RMA).

  • Page 31: Figure 2-1 Vmicpci-7715 Board Jumper Locations

    Hardware Setup Located On Reverse Side Figure 2-1 VMICPCI-7715 Board Jumper Locations...

  • Page 32: Table 2-1 Board Connectors

    No Boot Block Programming Boot Block Programming NOTE: The VMICPCI-7715’s BIOS has the capability (Default: Disabled) of password protecting casual access to the unit’s CMOS set-up screens. The Password Clear jumper (E24) allows for a means to clear the password feature, which might be necessary in the case of a forgotten password.

  • Page 33: Table 2-4 Password Clear (User Configurable) - Jumper (E24)

    Hardware Setup Table 2-4 Password Clear (User Configurable) - Jumper (E24) Jumper Position Normal Clear CMOS/Password Table 2-5 CMOS Battery Enable (User Configurable) - Jumper (E23) Jumper Position CMOS Battery Disabled CMOS Battery Enabled Table 2-6 Watchdog Battery Enable (User Configurable) - Jumper (E22) Jumper Position Watchdog Battery Disabled Watchdog Battery Enabled...

  • Page 34: Installation

    VMICPCI-7715: 1. Make sure power to the equipment is off. 2. If a PMC module such as VMIC’s VMIPMC-7441 is to be used, connect it to the VMICPCI-7715 prior to board installation. Refer to the Product Manual for that particular board for configuration and setup.

  • Page 35: Bios Setup

    The CMOS configuration controls many details concerning the behavior of the hardware from the moment power is applied. The VMICPCI-7715 is shipped from the factory with no hard drives configured in CMOS. The BIOS Setup program must be run to configure the specific drives attached.
  • Page 36 VMICPCI-7715 Product Manual...

  • Page 37: Chapter 3 - Pc/At Functions

    Because the design is PC/AT compatible, it retains standard PC memory and I/O maps along with standard interrupt architecture. Furthermore, the VMICPCI-7715 includes a PCI-compatible video adapter and Ethernet controller. The following sections describe in detail the PC/AT functions of the VMICPCI-7715.

  • Page 38: Cpu Socket

    The VMICPCI-7715 provides 512 Mbytes of Synchronous DRAM (SDRAM) as on-board system memory. Memory can be accessed as bytes, words or longwords. All RAM on the VMICPCI-7715 is dual-ported to the CompactPCI bus through the PCI-to-PCI bridge. The memory is addressable by the local processor, as well as the CompactPCI bus slave interface by another CompactPCI master.

  • Page 39: Memory And Port Maps

    Memory and Port Maps Memory Map The memory map for the VMICPCI-7715 is shown in Table 3-1. All systems share this same memory map, although a VMICPCI-7715 with less than the full 512 Mbyte of SDRAM does not fill the entire space reserved for On-Board Extended Memory.

  • Page 40: Table 3-2 Vmicpci-7715 I/O Address Map

    The BIOS initializes and configures all these registers properly; adjusting these I/O ports directly is not normally necessary. The assigned and user-available I/O addresses are summarized in the I/O Address Map, Table 3-2. Table 3-2 VMICPCI-7715 I/O Address Map I/O ADDRESS SIZE IN HW DEVICE...

  • Page 41: Pci-To-Pci Bridge

    $504 - $CFF Reserved * While these I/O ports are reserved for the listed functions, they are not implemented on the VMICPCI-7715. They are listed here to make the user aware of the standard PC/AT usage of these ports. PCI-to-PCI Bridge The VMICPCI-7715 uses the Intel 21154 PCI-to-PCI bridge to interface between the primary PCI bus of the unit and the CompactPCI (CPCI) bus.

  • Page 42: Pc/At Interrupts

    The interrupt number in HEX and decimal are also defined for real and protected mode in Table 3-4. The interrupt hardware implementation on the VMICPCI-7715 is standard for computers built around the PC/AT architecture, which evolved from the IBM PC/XT.
  • Page 43 PC/AT Interrupts Table 3-3 PC/AT Hardware Interrupt Line Assignments (Continued) AT FUNCTION COMMENTS Not Assigned Determined by BIOS Not Assigned Determined by BIOS Mouse Math Coprocessor AT Hard Drive Not Assigned Determined by BIOS Table 3-4 PC/AT Interrupt Vector Table INTERRUPT NO.
  • Page 44 VMICPCI-7715 Product Manual Table 3-4 PC/AT Interrupt Vector Table (Continued) INTERRUPT NO. REAL MODE PROTECTED MODE LINE BIOS Video I/O Coprocessor Error Eqpt Configuration Check Same as Real Mode Memory Size Check Same as Real Mode XT Floppy/Hard Drive Same as Real Mode...
  • Page 45 PC/AT Interrupts Table 3-4 PC/AT Interrupt Vector Table (Continued) INTERRUPT NO. REAL MODE PROTECTED MODE LINE DOS 3.x+ Network Comm Same as Real Mode DOS Internal Use Same as Real Mode DOS Internal Use Same as Real Mode DOS Internal Use Same as Real Mode DOS Internal Use Same as Real Mode...

  • Page 46: Pci Interrupts

    For a single function device, only INTA# may be used while the other three interrupt lines have no meaning. Figure 3-1 on page 47 depicts the VMICPCI-7715 interrupt logic pertaining to CompactPCI bus operations and the PCI expansion site.

  • Page 47: I/O Ports

    I/O Ports I/O Ports The VMICPCI-7715 incorporates the SMC Super-I/O chip. The SMC chip provides the VMICPCI-7715 with a standard floppy drive controller and two 16550 UART-compatible serial ports. The Ultra-IDE hard drive interface is provided by the Intel 82371EB (PIIX4E) PCI ISA IDE Xcelerator chip. All ports are present in their standard PC/AT locations using default interrupts.

  • Page 48: Video Graphics Adapter

    VMICPCI-7715 Product Manual Video Graphics Adapter The monitor port on the VMICPCI-7715 is controlled by a Chips and Technology 69030 video adapter chip with 4 Mbyte video SGRAM. The video controller chip is hardware and BIOS compatible with the IBM EGA and SXGA standards and also supports VESA high-resolution and extended video modes.

  • Page 49: Ethernet Controller

    A network based on the 10BaseT standard uses unshielded twisted-pair cables, providing an economical solution to networking by allowing the use of existing telephone wiring and connectors. 100BaseTx The VMICPCI-7715 also supports the 100BaseTx Ethernet. A network based on a 100BaseTx standard uses Category 5 unshielded twisted-pair cables.
  • Page 50 VMICPCI-7715 Product Manual...

  • Page 51: Chapter 4 - Embedded Pc/Rtos Features

    Smbus Multiplexer........... 70 Introduction VMIC’s VMICPCI-7715 features additional capabilities beyond those of a typical IBM PC/AT-compatible CPU. The unit provides three software-controlled, general purpose timers in addition to a programmable Watchdog Timer.

  • Page 52: Diskonchip (Optional)

    VMICPCI-7715 Product Manual DiskOnChip (Optional) The VMICPCI-7715 is available with an optional single DiskOnChip which is plugged into a standard 32-pin socket. The DiskOnChip is mapped into a 32 Kbyte window in the BIOS expansion address space of the PC, which is located between address 0xD0000 to 0xD1FFF.

  • Page 53: Using The Diskonchip With Other Operating Systems

    DiskOnChip (Optional) Using the DiskOnChip with Other Operating Systems If the VMICPCI-7715 is to be used with a DiskOnChip running an operating system other than DOS, the user should access the MSystems website at www.m-sys.com for information on installation and other details.

  • Page 54: Watchdog Timer

    The Time of Day feature found within the DS1384 device is explained in this section, but is not utilized by the VMICPCI-7715. The actual Time of Day registers used by the VMICPCI-7715 are located at the standard PC/AT I/O address. The Time of Day feature in the DS1384 Watchdog Timer is available for use by the user at their discretion.
  • Page 55 Watchdog Timer Table 4-1 Watchdog Registers Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Range $D8000 0.1 Seconds (BCD) 0.01 Seconds (BCD) 00 - 99 $D8001 10 Seconds (BCD) Seconds (BCD) 00 - 59 $D8002 10 Minutes (BCD)

  • Page 56: Time Of Day Registers

    VMICPCI-7715 Product Manual Time of Day Registers Registers 0, 1, 2, 4, 6, 8, 9 and A contain Time of Day data in BCD. Register 0 contains two Time of Day values. Bits 3 - 0 contain the 0.01 Seconds value with a range of 0 to 9 in BCD while Bits 7 - 4 contain the 0.1 Seconds value with a...

  • Page 57: Time Of Day Alarm Registers

    Watchdog Timer There are two techniques for reading the Time of Day from the Watchdog Timer. The first is to halt the external Time of Day registers from tracking the internal Time of Day registers by setting the Te bit (Bit 7 of the Command Register) to a logic zero (0), then reading the contents of the Time of Day registers.

  • Page 58: Watchdog Alarm Registers

    VMICPCI-7715 Product Manual Watchdog Alarm Registers Register C contains two Watchdog Alarm values. Bits 3 - 0 contain the 0.01 Seconds value with a range of 0 to 9 in BCD while Bits 7 - 4 contain the 0.1 Seconds value with a range of 0 to 9 in BCD.
  • Page 59 Watchdog Timer Tdm - Bit 2 Time of Day Alarm Mask - Enables/Disables the Time of Day Alarm to Interrupt Output when Ipsw (see Bit 6, Interrupt Switch) is set to logic one (1). When set to a logic zero (0), Time of Day Alarm Interrupt Output will be enabled. When set to a logic one (1), Time of Day Alarm Interrupt Output will be disabled.

  • Page 60: Timers

    VMICPCI-7715 Product Manual Timers General The VMICPCI-7715 provides a user-programmable 82C54 internal timer/counter. The 82C54 provides three independent, 16-bit timers, each operating at 1 or 2 MHz clock speed determined by the configuration of jumper E28. These timers are completely available to the user and are not dedicated to any PC/AT function.

  • Page 61: Clearing The Interrupt

    Timer Programming Architecture The VMICPCI-7715 Timers are mapped in I/O address space starting at $500. See Table 4-3. The Timers, consisting of three 16-bit timers and a Control Word Register (see Figure 4-5), are read from/written to via an 8-bit data bus.
  • Page 62 VMICPCI-7715 Product Manual Table 4-3 shows the I/O addresses of the Control Word Register and Timers. The Control Word Register is write only. The Timer status information can be obtained from the Read-Back command (see the “Reading” section on page 65).

  • Page 63: Writing

    Timers There are two 8-bit registers labeled TR and TR (Timer Register). The subscripts M and L stand for Most Significant byte and Least Significant byte. When a new count is written to the Timer, the count is loaded into the TR and later transferred to the TE. The Control logic lets one 8-bit TR register be written to at a time.

  • Page 64: Table 4-5

    VMICPCI-7715 Product Manual Table 4-5 ST - Select Timer ST1* ST0* Description Select Timer 0 Select Timer 1 Select Timer 2 page 65 Read-Back Command (See Reading section on *The ST bits specify which Timer (0, 1 or 2) the Control Word refers to or...

  • Page 65: Reading

    Timers Table 4-8 BCD BCD* Description Binary Timer 16-bits Binary Coded Decimal (BCD) Timer (4 Decades) * The BCD bit specifies whether the Timer count value is in Binary or BCD. When programming the 82C54, only two rules need to be followed. 1.

  • Page 66: Table 4-9

    VMICPCI-7715 Product Manual Read-Back Command The Read-Back Command allows the user to view the Timer count, the Timer Mode, the current state of the OUT pin, and the Load Flag of the selected Timer. Like a Control Word, the Read-Back Command is written into the Control Word Register and has the format shown in Tables 4-9 and 4-10.

  • Page 67: Table 4-13

    Timers Table 4-12 Status Byte Description Description D7: OUT Current state of Timers OUT pin D6: LOAD Count loaded into Timer D5-D0 Timer Programmed Mode Bit D7 contains the state of the Timers OUT pin. This allows viewing of the Timer’s OUT pin via software.

  • Page 68: Mode Definitions

    The VMICPCI-7715 utilizes an 82C54 Timer/Counter for its Timers. 82C54 Timer/Counters can be programmed to function in six different modes (numbered Mode 0 through Mode 5). The VMICPCI-7715 Timers are hardware configured to operate using Mode 2. Only Mode 2 is defined.

  • Page 69: Battery Backed Sram

    Battery Backed SRAM Battery Backed SRAM The VMICPCI-7715 includes 32 Kbytes of Nonvolatile SRAM addressed at $D8010 to $DFFFF. The lower 16 bytes, $D8000 to $D800F, are dedicated to the Watchdog Timer and the Board ID Register, and are unavailable for SRAM use. See the Watchdog Timer section.

  • Page 70: Smbus Multiplexer

    VMICPCI-7715 Product Manual Smbus Multiplexer The VMICPCI-7715 has an on-board Smbus. This Smbus is available through the CompactPCI J1 or J5 connector via a Phillips PCA9540 Smbus multiplexer. At power up this multiplexer is disabled. The Smbus multiplexer can be enabled and directed toward either the CompactPCI J1 or J5 connector by writing to the PCA9540 control register.

  • Page 71: Chapter 5 - Maintenance

    8. Quality of cables and I/O connections If products must be returned, obtain a RMA (Return Material Authorization) by contacting VMIC Customer Service. This RMA must be obtained prior to any return. VMIC Customer Service is available at: 1-800-240-7782. Or E-mail us at customer.service@vmic.com Maintenance Prints User level repairs are not recommended.
  • Page 72 VMICPCI-7715 Product Manual...

  • Page 73: Appendix A - Connector Pinouts

    PMC J6 Connector Pinout..........81 Introduction The VMICPCI-7715 PC/AT-Compatible CompactPCI Controller has all I/O distributed through CompactPCI J2, J4 and J5 connectors.

  • Page 74: Figure A-1 Vmicpci-7715 Connector Locations

    VMICPCI-7715 Product Manual Located On Reverse Side Figure A-1 VMICPCI-7715 Connector Locations...

  • Page 75: J1 Connector Pinout

    J1 Connector Pinout J1 Connector Pinout The VMICPCI-7715 utilizes a high-density 110-pin, low inductance, and controlled impedance connector. This connector meets the IEC-1076 international standard for CompactPCI connectors. An additional external metal shield is required. The large number of ground pins ensures adequate shielding and grounding for low ground bounce and reliable operation in noisy environments.

  • Page 76: J2 Connector Pinout

    VMICPCI-7715 Product Manual J2 Connector Pinout The VMICPCI-7715 J2 connector is a 2mm “Hard Metric” CompactPCI connector, with five rows of 22 pins each. J2 is required for system slot CPUs. An additional external metal shield is also used, labeled row F. This connector’s controlled impedance minimizes unwanted signal reflections.

  • Page 77: J4 Connector Pinout

    J4 Connector Pinout J4 Connector Pinout The VMICPCI-7715 J4 connector is a 2mm “Hard Metric” CompactPCI connector, with five rows of 25 pins each. An additional external metal shield is also used. This connector’s controlled impedance minimizes unwanted signal reflections. Figure A-4 illustrates the J4 connector and the connector pinout.

  • Page 78: J5 Connector Pinout

    VMICPCI-7715 Product Manual J5 Connector Pinout The VMICPCI-7715 J5 connector is a 2mm “Hard Metric” CompactPCI connector, with 5 rows of 22 pins each. An additional external metal shield is also used, labeled row F. This connector’s controlled impedance minimizes unwanted signal reflections.

  • Page 79: Pmc J7 Connector Pinout

    PMC J7 Connector Pinout PMC J7 Connector Pinout The PCI Mezzanine Card (PMC) carries the same signals as the PCI standard; however, the PMC standard uses a completely different form factor. Tables A-1 through A-3 are the pinouts for the PMC connectors (J6, J7and J8). Table A-1 PMC J7 Connector Pinout PMC Connector (J7) PMC Connector (J7)

  • Page 80: Pmc J8 Connector Pinout

    VMICPCI-7715 Product Manual PMC J8 Connector Pinout Table A-2 PMC J8 Connector Pinout PMC Connector (J8) PMC Connector (J8) Left Side Right Side Left Side Right Side Name Name Name Name +12 V +5 V TRDY +3.3 V +5 V...

  • Page 81: Pmc J6 Connector Pinout

    PMC J6 Connector Pinout PMC J6 Connector Pinout Table A-3 PMC J6 Connector Pinout PMC Connector (J6) PMC Connector (J6) Left Side Right Side Left Side Right Side Name Name Name Name PMC_I/O_1 PMC_I/O_2 PMC_I/O_33 PMC_I/O_34 PMC_I/O_3 PMC_I/O_4 PMC_I/O_35 PMC_I/O_36 PMC_I/O_5 PMC_I/O_6 PMC_I/O_37...
  • Page 82 VMICPCI-7715 Product Manual...

  • Page 83: Appendix B - System Driver Software

    Driver Software Installation In order to properly use the Video and LAN adapters of the VMICPCI-7715, the user must install the driver software located on the distribution diskettes provided with the unit. Detailed instructions for installation of the drivers during installation of Windows 2000 or Windows NT (Versions 4.0) operating systems are described in the...

  • Page 84: Windows 2000

    6. Select Next to continue. 7. Ensure Search For Suitable Driver For My Device is selected then Click Next. 8. Click in the box next to Floppy Disk Drives and ensure VMIC’s disk 320-500076-003 is inserted in the floppy drive, then click Next.
  • Page 85 Windows 2000 9. The Drivers File Search Results window should identify GD82559ER PCI Adapter as the driver it found. Select Next to continue. 10. The Digital Signature Not Found box indicates this is not a Microsoft driver. Select Yes to continue 11.

  • Page 86: Windows Nt (Version 4.0)

    VMICPCI-7715 Product Manual Windows NT (Version 4.0) Windows NT 4.0 includes drivers for the on-board LAN, and video adapters. The following steps are required to configure the LAN for operation. 1. Follow the normal Windows NT 4.0 installation until you reach the Windows NT Workstation Setup window which states that Windows NT Needs To Know How This Computer Should Participate On A Network.
  • Page 87 Windows NT (Version 4.0) 20. Select the Settings tab in the Display Properties window, then click the Display Type button. 21. In the Display Type window, click Change. 22. In the Change Display window, click Have Disk. 23. Insert disk 320-500076-002 into drive A. 24.
  • Page 88 VMICPCI-7715 Product Manual...

  • Page 89: Appendix C - Phoenix Bios

    Exit Menu ............101 Introduction The VMICPCI-7715 utilizes the BIOS (Basic Input/Output System) in the same manner as other PC/AT compatible computers. This appendix describes the menus and options associated with the VMICPCI-7715 BIOS.

  • Page 90: Main Menu

    VMICPCI-7715 Product Manual Main Menu The Main menu allows the user to select QuickBoot, set the system clock and calendar, record disk drive parameters, and set selected functions for the keyboard. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ H6DI 6q‰hprq Q‚r… 7‚‚‡ @‘v‡ D‡r€ÃTƒrpvsvpÃCryƒ Rˆvpx7‚‚‡ÃH‚qr) b@hiyrqd T’†‡r€ÃUv€r)

  • Page 91: Legacy Diskette

    The VMICPCI-7715 does not support a second floppy drive. The default is Disabled. Primary Master/Slave The VMICPCI-7715 is capable of utilizing one IDE hard disk drive on the Primary Master bus. The default setting is Auto. The Primary Slave is assigned to the CD-ROM (if installed).

  • Page 92: Secondary Master

    VMICPCI-7715 Product Manual Secondary Master The Secondary Master is the resident Flash Disk (if installed). The default setting is None. Keyboard Features The Keyboard Features allows the user to set several keyboard functions. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ H6DI D‡r€ÃTƒrpvsvpÃCryƒ Fr’i‚h…qÃArh‡ˆ…r† Tryrp‡†ÃQ‚r…‚Ã†‡h‡r Iˆ€G‚px) bPssd s‚…ÃIˆ€G‚px...

  • Page 93: Keyboard Auto-Repeat Delay (Sec)

    Main Menu Keyboard Auto-Repeat Delay (sec) If the Key Click is enabled this determines the delay before a character starts repeating when a key is held down. The options are: 1/4, 1/2, 3/4, or 1 second. The default is 1/2. Keyboard Test This feature will test the keyboard during boot-up.

  • Page 94: Com Port Address

    VMICPCI-7715 Product Manual Com Port Address If enabled, it will allow remote access through the serial port. The options are: Disabled, Motherboard Com A and Motherboard Com B. The default is Disabled. Baud Rate Selects a baud rate for the serial port. The options are: 600, 1200, 2400, 4800, 9600, 19.2, 38.4 and 115.2.

  • Page 95: Advanced Menu

    Advanced Menu Advanced Menu Selecting Advanced from the Main menu will display the screen shown below. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ Hhv 69W6I8@9 Q‚r… 7‚‚‡ @‘v‡ D‡r€ÃTƒrpvsvpÃCryƒ D†‡hyyrqÃPT) bP‡ur…– 68QD) b9v†hiyrqd Tryrp‡Ã‡urƒr…h‡vt Sr†r‡Ã8‚svtˆ…h‡v‚Ã9h‡h) bI‚d †’†‡r€Ãv†‡hyyrq ‚Ã’‚ˆ…Æ’†‡r€Ãuvpu # 8hpurÃHr€‚…’ ’‚ˆÃvyyȆrÀ‚†‡ # DPÃ9r‰vprÃ8‚svtˆ…h‡v‚ p‚€€‚y’ Gh…trÃ9v†xÃ6ppr††ÃH‚qr) b9PTd G‚phyÃ7ˆ†ÃD9@Ãhqhƒ‡r…) bQ…v€h…’d # 6q‰hprqÃ8uvƒ†r‡Ã8‚‡…‚y)

  • Page 96: I/O Device Configuration

    VMICPCI-7715 Product Manual Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ 69W6I8@9 D‡r€ÃTƒrpvsvpÃCryƒ 8hpurÃHr€‚…’ Tr‡†Ã‡urƇh‡rÂsÇur Hr€‚…’Ã8hpur b@hiyrqd €r€‚…’Ãphpur 8hpurÃT’†‡r€Ã7DPTÃh…rh) bX…v‡rÃQ…‚‡rp‡d 8hpurÃWvqr‚Ã7DPTÃh…rh) bX…v‡rÃQ…‚‡rp‡d 8hpurÃ7h†rÃ$ !x) bX…v‡rÃ7hpxd 8hpurÃ7h†rÃ$ !x%#x) bX…v‡rÃ7hpxd 8hpurÃ@‘‡rqrqÃHr€‚…’Ã6…rh) bX…v‡rÃ7hpxd 8hpurÃ66AAA) b9v†hiyrqd 8hpurÃ77AAA) b9v†hiyrqd 8'87AA) b9v†hiyrqd 888AAA) b9v†hiyrqd 99"AA) b9v†hiyrqd 9#9&AA) b9v†hiyrqd 9'97AA) b9v†hiyrqd 989AAA) b9v†hiyrqd Cryƒ...

  • Page 97: Large Disk Access Mode

    Advanced Menu Large Disk Access Mode The options for the Large Disk Access Mode are UNIX Novell Netware or Other. If you are installing new software and the drive fails, change this selection and try again. Different operating systems require different representations of drive geometries.

  • Page 98: Enable Memory Gap

    VMICPCI-7715 Product Manual Enable Memory Gap If enabled, turn system RAM off to free address space for use with an option card. Either a 128kB conventional memory gap, starting at 512kB, or an extended memory gap, starting at 15MB, will be created in system RAM.

  • Page 99: Power

    Power Power This screen, selected from the Main screen, allows the user to configure power saving options on the VMICPCI-7715. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ Hhv 6q‰hprq QPX@S 7‚‚‡ @‘v‡ D‡r€ÃTƒrpvsvpÃCryƒ Q‚r…ÃTh‰vt†) b9v†hiyrqd Hh‘v€ˆ€ÃQ‚r…Æh‰vt† HhˆhyÃ8QVÃ8y‚pxÃUu…‚‡‡yvtÃÈ) b9v†hiyrqd p‚†r…‰r†Ã‡urÃt…rh‡r†‡ 8QVÃUu…‚‡‡yvtÃq‚Ã‡u…r†u‚yq) b9v†hiyrqd h€‚ˆ‡Ã‚sÆ’†‡r€Ãƒ‚r… Hh‘v€ˆ€ÃQr…s‚…€hpr T‡hqi’ÃUv€r‚ˆ‡) bPssd p‚†r…‰r†Ãƒ‚r…Ãiˆ‡...

  • Page 100: Boot Menu

    VMICPCI-7715 Product Manual Boot Menu The Boot priority is determined by the stack order, with the top having the highest priority and the bottom the least. The order can be modified by highlighting a device and, using the <+> or <-> keys, moving it to the desired order in the stack. A device can be boot disabled by highlighting the particular device and pressing <Shift 1>.

  • Page 101: Exit Menu

    Exit Menu Exit Menu The Exit menu allows the user to exit the BIOS program, while either saving or discarding any changes. This menu also allows the user to restore the BIOS defaults if desired. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ @‘v‡ Hhv 6q‰hprq Q‚r… 7‚‚‡...
  • Page 102 VMICPCI-7715 Product Manual...

  • Page 103: Appendix D - Lanworks Bios

    BIOS Features Setup ..........106 Introduction The VMICPCI-7715 includes a LANWorks option which allows the VMICPCI-7715 to be booted from a network. This appendix describes the procedures to enable this...

  • Page 104: Boot Menus

    First Boot menu. Selecting “Managed PC Boot Agent (MBA)” to boot from the LAN in this screen applies to the current boot only, at the next reboot the VMICPCI-7715 will revert back to the setting in the Boot menu.
  • Page 105 Boot Menus Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ 7‚‚‡ H6DI 6q‰hprq Trpˆ…v‡’ Q‚r… @‘v‡ D‡r€ÃTƒrpvsvpÃCryƒ HhhtrqÃQ8Ã7‚‚‡Ã6tr‡ÃH76 ÃSr€‚‰hiyrÃ9r‰vpr†) Fr’†Ãˆ†rqÇ‚ÉvrÃ‚… ÃCh…qÃ9…v‰r p‚svtˆ…rÃqr‰vpr†) ÃÃ6U6QDÃ89SPHÃ9…v‰r 1@‡r…3Ãr‘ƒhq†Ã‚… ÃSr€‚‰hiyrÃ9r‰vpr†) p‚yyhƒ†r†Ãqr‰vpr†Ãv‡u hÃÂ…Ã 18‡…yÃÃ@‡r…3Ãr‘ƒhq† hyy 1Tuvs‡Ãà 3Ãrhiyr†Ã‚… qv†hiyr†ÃhÃqr‰vpr 13ÃhqÃ13À‚‰r†Ã‡urà qr‰vprȃÂ…Ãq‚ 13Àh’À‚‰rÃ…r€‚‰hiyr qr‰vprÃir‡rrÃCh…qà 9v†xÂ…ÃSr€‚‰hiyrÃ9v†x 1q3Ã…r€‚‰rÃhÃqr‰vpr ‡uh‡Ãv†Ã‚‡Ãv†‡hyyrq A Cryƒ Tryrp‡ÃD‡r€8uhtrÃWhyˆr†A(Tr‡ˆƒÃ9rshˆy‡† ↑ ↓ @T8@‘v‡ Tryrp‡ÃHrˆ@‡r…Tryrp‡Ã#ÃTˆiHrˆA Th‰rÃhqÃ@‘v‡ ←...

  • Page 106: Bios Features Setup

    VMICPCI-7715 Product Manual BIOS Features Setup After the Managed PC Boot Agent has been enabled there are several boot options available to the user. These options are RPL (default), TCP/IP, Netware, and PXE. The screens below show the defaults for each boot method.

  • Page 107: Netware

    BIOS Features Setup Netware HhhtrqÃQ8Ã7‚‚‡Ã6tr‡ÃH76É"!Ã7DPTÃD‡rt…h‡rq pÃ8‚ƒ’…vtu‡Ã (('ÃG6IX‚…x†ÃUrpu‚y‚tvr†Ã8‚Ãhƈi†vqvh…’ÂsÃ"8‚€Ã8‚…ƒ‚…h‡v‚ 6yyÃ…vtu‡†Ã…r†r…‰rq 8‚svtˆ…h‡v‚ 7‚‚‡ÃHr‡u‚q) Ir‡h…r Q…‚‡‚p‚y '!! 8‚svtÃHr††htr) @hiyrq Hr††htrÃUv€r‚ˆ‡) %ÃTrp‚q† 7‚‚‡Ãshvyˆ…rÃQ…‚€ƒ‡) Xhv‡Ãs‚…Ãxr’ 7‚‚‡ÃAhvyˆ…r) Ir‘‡Ã77TÃqr‰vpr V†rÃpˆ…†‚…Ãxr’†Ã‡‚Ãrqv‡)ÃVƒ9‚ÃpuhtrÃsvryqÃGrs‡Svtu‡ÃpuhtrÉhyˆr @T8ǂĈv‡ÃA(Ã…r†‡‚…rÃ…r‰v‚ˆ†Ã†r‡‡vt†ÃA Ç‚Æh‰r HhhtrqÃQ8Ã7‚‚‡Ã6tr‡ÃH76É"!Ã7DPTÃD‡rt…h‡rq pÃ8‚ƒ’…vtu‡Ã (('ÃG6IX‚…x†ÃUrpu‚y‚tvr†Ã8‚Ãhƈi†vqvh…’ÂsÃ"8‚€Ã8‚…ƒ‚…h‡v‚ 6yyÃ…vtu‡†Ã…r†r…‰rq 8‚svtˆ…h‡v‚ 7‚‚‡ÃHr‡u‚q) V†rÃpˆ…†‚…Ãxr’†Ã‡‚Ãrqv‡)ÃVƒ9‚ÃpuhtrÃsvryqÃGrs‡Svtu‡ÃpuhtrÉhyˆr @T8ǂĈv‡ÃA(Ã…r†‡‚…rÃ…r‰v‚ˆ†Ã†r‡‡vt†ÃA Ç‚Æh‰r...
  • Page 108 VMICPCI-7715 Product Manual...

  • Page 109: Appendix E - Device Configuration: I/O And Interrupt Control

    This appendix provides the information needed to develop custom applications for the VMICPCI-7715. The CPU board on the VMICPCI-7715 is unique in that the BIOS cannot be removed; it must be used in the initial boot cycle. A custom application, like a revised operating system for example, can only begin to operate after the BIOS has finished initializing the CPU.

  • Page 110: Bios Operations

    BIOS and reconfigure the system, or it may accept what the BIOS initialized. BIOS Control Overview There are two areas on the VMICPCI-7715 in which the user must be familiar in order to override the initial BIOS configuration. These areas include the device addresses and the device interrupts.

  • Page 111: Figure E-1 Vmicpci-7715 Block Diagram

    EIDE Philips PCA9540 Hard COM Port 1 Drive DiskOnChip COM Port 2 Socket Optional SUPER 16 Bit Timers with 82C54 Flash BIOS Watchdog Timer Floppy Drive DS1384 FDC37C67X Non Volatile SRAM PS/2 Keyboard / Mouse Figure E-1 VMICPCI-7715 Block Diagram...

  • Page 112: Data Book References

    VMICPCI-7715 Product Manual Data Book References 1. Pentium III Processor Developer’s Manual Order Number 241428 Intel Corporation 2200 Mission College Blvd. P.O. Box 58119 Santa Clara, CA 95052-8119 (408) 765-8080 www.intel.com 2. Intel 440BX PCISet 82443BX Host Bridge/Controller Intel Corporation 2200 Mission College Blvd.
  • Page 113 BIOS Operations 8. ISA & EISA, Theory and Operation Solari, Edward Annabooks 15010 Avenue of Science, Suite 101 San Diego, CA 92128 USA ISBN 0-929392 -15-9 9. DS 1384 Watchdog Timekeeping Controller Dallas Semiconductor 4461 South Beltwood Pwky. Dallas, TX 75244-3292 10.

  • Page 114: Device Address Definition

    64 Kbyte. ISA Devices The ISA devices on the VMICPCI-7715 are configured by the BIOS at boot-up and adhere to the standard PC/AT architecture. They are mapped in I/O address space within standard addresses and their interrupts are mapped to standard interrupt control registers.

  • Page 115: Pci Devices

    Device Address Definition PCI Devices PCI devices are fully configured under I/O and/or Memory address space. Table E-2 describes the on-board PCI bus devices and each device’s configuration spectrum. The PCI bus includes three physical address spaces. As with ISA bus, PCI bus supports Memory and I/O address space, but PCI bus includes an additional Configuration address space.

  • Page 116: Device Interrupt Definition

    ISA Device Interrupt Map The VMICPCI-7715 BIOS maps the IRQx lines to the appropriate device per the standard ISA architecture. Reference Figure E-2 on page 117. This initialization operation cannot be changed; however, a custom application could reroute the...

  • Page 117: Figure E-2 Bios Default Connections For The Pc Interrupt Logic Controller

    Device Interrupt Definition 8259 MASTER- PORTS $020-$021 Interrupt Com 2 Com 1 Floppy Timer Keybd 8-15 Control Timers IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 8259 SLAVE- PORTS $0A0-$0A1 Real-Tm Mouse Math Hard Drv Clock Coproc IRQ8 IRQ9 IRQ11 IRQ12 IRQ13 IRQ14...

  • Page 118: Pci Device Interrupt Map

    VMICPCI-7715 Product Manual PCI Device Interrupt Map The PCI bus-based external devices include the two PCI expansion sites, the PCI-to-PCIbus bridge and the SVGA reserved connection. The default BIOS maps these external devices to the PCI Interrupt Request (PIRQx) lines of the PIIX4E. This mapping is illustrated in Figure E-2 on page 117 and is defined in Table E-3.

  • Page 119: Appendix F - Sample C Software

    Introduction This appendix provides listings of a library of sample code that the programmer may utilize to build applications. These files are provided to the VMICPCI-7715 user on disk 320-500076-007, Sample Application C Code for the VMICPCI-7715, included in the distribution disk set.

  • Page 120: Directory Cpu

    VMICPCI-7715 Product Manual Directory CPU The code under the CPU directory sets up the universe chip with one PCI-TO-VME window and enables universe registers to be accessed from VME to allow mailbox access. CPU.C /****************************************************************************/ FILE: CPU.C Setup the universe chip with one PCI-TO-VME window and enable universe registers to be accessed from VME to allow mailbox access.
  • Page 121 Directory CPU unsigned long mb3_msg; unsigned long int_status; void far interrupt (* old_vect)(void); unsigned char int_line; char user[80]; FPTR un_regs; void main( void ) unsigned char pci_devices; int test_int, to_cnt; unsigned long temp_dword; unsigned char bus, dev_func; printf(“\n\n”); /* try to locate the UNIVERSE device on the PCI bus */ test_int = find_pci_device(UNIVERSE_DID, UNIVERSE_VID, 0, &bus, &dev_func);...
  • Page 122 VMICPCI-7715 Product Manual exit( 1 ); /* setup protected mode */ extend_seg(); a20( 1 ); mb0_msg = 0; mb1_msg = 0; mb2_msg = 0; mb3_msg = 0; init_int(); /* 32K PCI slave window at 0x10000000 to VME A16 0x0000 user data */ fw_long( un_regs + LSI0_BS_A, PCI_BASE16 );...
  • Page 123 Directory CPU restore_orig_int( ); a20( 0 ); exit( xcode ); } /* end do_exit */ /*******************************************************************/ init_int() purpose: Using the interrupt assigned, the original vector is saved and the vector to the new ISR is installed. The */ programmable-interrupt-controller (PIC) is enabled. /*******************************************************************/ parameters: none /*******************************************************************/...
  • Page 124 VMICPCI-7715 Product Manual /* enable interrupt 12 */ outp(0xa1, (pic2_org & 0xEF) ); break; case 0xd: old_vect = getvect( IRQD ); /* save vector for IRQ 13 */ setvect( IRQD, irq_rcvd ); /* enable interrupt 13 */ outp(0xa1, (pic2_org & 0xDF) );...
  • Page 125 Directory CPU return value: none /*******************************************************************/ void restore_orig_int( void ) disable(); outp(0xa1, pic2_org); switch( int_line ) case 0x9: setvect( IRQ9, old_vect ); break; case 0xa: setvect( IRQA, old_vect ); break; case 0xb: setvect( IRQB, old_vect ); break; case 0xc: setvect( IRQC, old_vect ); break;...
  • Page 126 VMICPCI-7715 Product Manual void interrupt irq_rcvd( void ) unsigned long lint_enable, tmp_status; disable(); asm { .386P push push int_status = fr_long( un_regs + LINT_STAT_A ); /* read interrupt status */ fw_long( un_regs + LINT_STAT_A, int_status ); /* clear status */ /* check for mailbox interrupt */ if( int_status &...
  • Page 127 Directory CPU outp(0x20, 0x20); /* Master end of irq command */ outp(0xa0, 0x20); /* Slave end of irq command */ asm { .386P enable();...

  • Page 128: File: Cpu.h

    VMICPCI-7715 Product Manual ** FILE: CPU.H typedef unsigned char Byte; typedef unsigned short Word; typedef unsigned long Long; /* universe Device ID and Vendor ID */ #define UNIVERSE_VID 0x10E3 #define UNIVERSE_DID 0x0000 /* CPU specific bits located at I/O 0x400 */...

  • Page 129: File: Flat.c

    Directory CPU ** FILE: FLAT.C flat.c Access flat memory space (up to 4GB) in real mode. #include <stdio.h> #include <dos.h> #include “flat.h” Keyboard controller defines #define RAMPORT 0x70 #define KB_PORT 0x64 #define PCNMIPORT 0xA0 #define INBA20 0x60 #define INBA20ON 0xDF #define INBA20OFF 0xDD...
  • Page 130 VMICPCI-7715 Product Manual void far * linear_to_seg( FPTR lin ) void far *p; FP_SEG(p) = (unsigned int)( lin >> 4 ); FP_OFF(p) = (unsigned int)( lin & 0xF ); return p; Adjust the GS register’s limit to 4GB Note: interrupts are enabled by this call.
  • Page 131 Directory CPU push bx,address lgdt FWORD ptr [bx] eax,cr0 al,0x01 cr0,eax short nxt nxt: asm { .386P bx,8 gs,bx es,bx al,0xfe cr0,eax int fr_byte( FPTR adr ) int d; asm { .386P ax,ax /* zero gs */ gs,ax eax, adr al,byte ptr gs:[eax] d,ax return d;...
  • Page 132 VMICPCI-7715 Product Manual long fr_long( FPTR adr ) long asm { .386P ax,ax /* zero gs */ gs,ax eax,adr eax,dword ptr gs:[eax] d,eax return d; void fw_byte( FPTR a, int d ) asm { .386P ax,ax /* zero gs */...
  • Page 133 Directory CPU dword ptr gs:[eax],ebx /* flat move long */ void fml_string( FPTR d, FPTR s, long n ) asm { .386P /* have to use ES for string move */ push es /* save es */ ax,ax /* zero gs */ gs,ax es,ax edi,d...
  • Page 134 VMICPCI-7715 Product Manual edi,d /* This is the destination pointer */ esi,s /* This is the source pointer */ ecx,n /* This is the number of bytes */ rep movs byte ptr es:[edi],byte ptr gs:[esi] pop es /* give back es */...

  • Page 135: File: Flat.h

    Directory CPU ** FILE: FLAT.H flat.h ** Prototypes typedefs and macros for flat memory access typedef unsigned long FPTR; Global descriptor table struct _GDT { unsigned int limit; unsigned int base; unsigned int access; unsigned int hi_limit; static struct _GDT GDT[2]= { {0,0,0,0}, /* Null selector slot */ {0xFFFF,0,0x9200,0x8F}...
  • Page 136 VMICPCI-7715 Product Manual void fmw_string( FPTR, FPTR, long ); /* flat move word */ void fmb_string( FPTR, FPTR, long ); /* flat move byte */...

  • Page 137: File: Pci.c

    Directory CPU ** FILE: PCI.C #include <dos.h> #include <stddef.h> #include “pci.h” #define HIGH_BYTE(ax) (ax >> 8) #define LOW_BYTE(ax) (ax & 0xff) int find_pci_device(unsigned short device_id, unsigned short vendor_id, unsigned short index, unsigned char *bus_number, unsigned char *device_and_function) int ret_status; unsigned short ax, bx, flags; _CX = device_id;...
  • Page 138 VMICPCI-7715 Product Manual int ret_status; unsigned short ax, flags; unsigned long ecx; _BH = bus_number; _BL = device_and_function; _DI = register_number; _AH = PCI_FUNCTION_ID; _AL = function; geninterrupt(0x1a); ecx = _ECX; ax = _AX; flags = _FLAGS; if ((flags & CARRY_FLAG) == 0) ret_status = HIGH_BYTE(ax);...
  • Page 139 Directory CPU if ((flags & CARRY_FLAG) == 0) ret_status = HIGH_BYTE(ax); else ret_status = NOT_SUCCESSFUL; return(ret_status); void outpd(unsigned short port, unsigned long value) _DX = port; _EAX = value; __emit__(0x66, 0xEF); unsigned long inpd(unsigned short port) _DX = port; __emit__(0x66, 0xED); return(_EAX);...

  • Page 140: File: Pci.h

    VMICPCI-7715 Product Manual ** FILE: PCI.H #define TRUE 1 #define FALSE 0 #define CARRY_FLAG 0x01 /* PCI Functions */ #define PCI_FUNCTION_ID 0xB1 #define PCI_BIOS_PRESENT 0x01 #define FIND_PCI_DEVICE 0x02 #define FIND_PCI_CLASS_CODE 0x03 #define READ_CONFIG_BYTE 0x08 #define READ_CONFIG_WORD 0x09 #define READ_CONFIG_DWORD 0x0A...

  • Page 141: File: Universe.h

    Directory CPU ** FILE: UNIVERSE.H file: universe.h header file for the universe II chip register definitions typedef volatile struct universe_regs { unsigned long pci_id; /* PCI device ID vendor ID unsigned long pci_csr; /* PCI config control/status reg unsigned long pci_class; /* PCI config class reg unsigned long pci_misc0;...
  • Page 142 VMICPCI-7715 Product Manual unsigned long scyc_addr; /* PCI special cycle PCI address reg unsigned long scyc_en; /* PCI special cycle swap/compare enable reg unsigned long scyc_cmp; /* PCI special cycle compare data reg unsigned long scyc_swp; /* PCI special cycle swap data reg unsigned long lmisc;...
  • Page 143 Directory CPU unsigned long vint_en; /* VME interrupt enable unsigned long vint_stat; /* VME interrupt status unsigned long vint_map0; /* VME interrupt map0 unsigned long vint_map1; /* VME interrupt map1 unsigned long statid; /* VME interrupt status/ID out unsigned long v1_statid; /* VME interrupt status/ID in IRQ1 unsigned long v2_statid;...
  • Page 144 VMICPCI-7715 Product Manual unsigned long vsi3_to; /* VMEbus slave image 3 translation offset unsigned long urI[0x06]; /* reserved unsigned long lm_ctl; /* Location Monitor Control unsigned long lm_bs; /* Location Monitor Base Address unsigned long urJ; /* reserved unsigned long vrai_ctl;...
  • Page 145 Directory CPU #define LSI0_CTL_A 0x100 /* PCI slave image 0 control reg #define LSI0_BS_A 0x104 /* PCI slave image 0 base address reg #define LSI0_BD_A 0x108 /* PCI slave image 0 bound address reg #define LSI0_TO_A 0x10C /* PCI slave image 0 translation offset reg #define LSI1_CTL_A 0x114...
  • Page 146 VMICPCI-7715 Product Manual #define DVA_A 0x210 /* DMA VMEbus address reg #define DCPP_A 0x218 /* DMA command packet pointer #define DGCS_A 0x220 /* DMA general control and status reg #define D_LLUE_A 0x224 /* DMA linked list update enable reg #define...
  • Page 147 Directory CPU #define VSI3_CTL_A 0xF3C /* VMEbus slave image 3 control reg #define VSI3_BS_A 0xF40 /* VMEbus slave image 3 base address reg #define VSI3_BD_A 0xF44 /* VMEbus slave image 3 bound address reg #define VSI3_TO_A 0xF48 /* VMEbus slave image 3 translation offset #define LM_CTL_A 0xF64...
  • Page 148 VMICPCI-7715 Product Manual unsigned long rsvd1; /* RESERVED unsigned long dma_dva; /* DMA VMEbus address reg unsigned long rsvd2; /* RESERVED unsigned long dma_dcpp; /* DMA command packet pointer reg unsigned long rsvd3; /* RESERVED } dma_cmd_pkt_t; /* pci_id - PCI device ID and vendor ID */...
  • Page 149 Directory CPU #define PCI_MISC1_MAX_LAT 0x00000000 /* R maximum latency: none #define PCI_MISC1_MAX_GNT 0x00030000 /* R minimum grant: 250 ns #define PCI_MISC1_INT_PIN 0x00000100 /* R interrupt pin #define PCI_MISC1_INT_LINE 0x000000FF /* R/W interrupt line MASK /* LSI[X]_ctl - slave image control registers ( lsi0 - lsi7 ) */ #define LSI_CTL_EN 0x80000000...
  • Page 150 VMICPCI-7715 Product Manual #define LSI6_BD 0xFFFF0000 /* R/W PCI slave image 6 bound addr MASK #define LSI7_BD 0xFFFF0000 /* R/W PCI slave image 7 bound addr MASK /* lsi[X]_to - slave image 0/1/2/3/4/5/6/7 translation offset reg 0x0000?XXX */ #define LSI0_TO...
  • Page 151 Directory CPU #define SLSI_VDW 0x00F00000 /* R/W VME max data width MASK #define SLSI_PGM 0x0000F000 /* R/W VME program/data AM code MASK #define SLSI_SUPER 0x00000F00 /* R/W VME supervisor/user AM code MASK #define SLSI_BS 0x000000FC /* R/W base address MASK #define SLSI_LAS_M 0x00000000...
  • Page 152 VMICPCI-7715 Product Manual #define DGCS_GO 0x80000000 /* R0/W DMA go bit #define DGCS_STOP_REQ 0x40000000 /* R0/W DMA stop request #define DGCS_HALT_REQ 0x20000000 /* R0/W DMA halt request #define DGCS_CHAIN 0x08000000 /* R/W DMA chaining #define DGCS_VON1 0x00000000 /* R/W VME aligned DMA xfer cnt DONE...
  • Page 153 Directory CPU #define LINT_EN_MBOX2 0x00040000 /* R/W MAILBOX 2 enable #define LINT_EN_MBOX1 0x00020000 /* R/W MAILBOX 1 enable #define LINT_EN_MBOX0 0x00010000 /* R/W MAILBOX 0 enable #define LINT_EN_ACFAIL 0x00008000 /* R/W ACFAIL interrupt enable #define LINT_EN_SYSFAIL 0x00004000 /* R/W SYSFAIL interrupt enable #define LINT_EN_SW_INT 0x00002000...
  • Page 154 VMICPCI-7715 Product Manual #define LINT_MAP0_VIRQ7_1 0x10000000 /* R/W PCI int LINT#1 for VME IRQ7 #define LINT_MAP0_VIRQ7_2 0x20000000 /* R/W PCI int LINT#2 for VME IRQ7 #define LINT_MAP0_VIRQ7_3 0x30000000 /* R/W PCI int LINT#3 for VME IRQ7 #define LINT_MAP0_VIRQ7_4 0x40000000 /* R/W PCI int LINT#4 for VME IRQ7...
  • Page 155 Directory CPU #define LINT_MAP0_VIRQ2_5 0x00000500 /* R/W PCI int LINT#5 for VME IRQ2 #define LINT_MAP0_VIRQ2_6 0x00000600 /* R/W PCI int LINT#6 for VME IRQ2 #define LINT_MAP0_VIRQ2_7 0x00000700 /* R/W PCI int LINT#7 for VME IRQ2 #define LINT_MAP0_VIRQ1_0 0x00000000 /* R/W PCI int LINT#0 for VME IRQ1 #define LINT_MAP0_VIRQ1_1 0x00000010 /* R/W PCI int LINT#1 for VME IRQ1 #define...
  • Page 156 VMICPCI-7715 Product Manual #define LINT_MAP1_SW_IACK_0 0x00000000 /* R/W PCI int LINT#0 for SW_IACK #define LINT_MAP1_SW_IACK_1 0x00010000 /* R/W PCI int LINT#1 for SW_IACK #define LINT_MAP1_SW_IACK_2 0x00020000 /* R/W PCI int LINT#2 for SW_IACK #define LINT_MAP1_SW_IACK_3 0x00030000 /* R/W PCI int LINT#3 for SW_IACK...
  • Page 157 Directory CPU #define VINT_EN_SW_IACK 0x00001000 /* R/W enable VMEbus int SW_IACK #define VINT_EN_VERR 0x00000400 /* R/W enable PCIbus int VERR #define VINT_EN_LERR 0x00000200 /* R/W enable PCIbus int LERR #define VINT_EN_DMA 0x00000100 /* R/W enable PCIbus int DMA #define VINT_EN_LINT7 0x00000080 /* R/W enable PCIbus int LINT7 #define VINT_EN_LINT6...
  • Page 158 VMICPCI-7715 Product Manual #define VINT_MAP0_LINT7_7 0x70000000 /* R/W VME int 7 for LINT7 #define VINT_MAP0_LINT6_D 0x00000000 /* R/W VME int disable for LINT6 #define VINT_MAP0_LINT6_1 0x01000000 /* R/W VME int 1 for LINT6 #define VINT_MAP0_LINT6_2 0x02000000 /* R/W VME int 2 for LINT6...
  • Page 159 Directory CPU #define VINT_MAP0_LINT1_3 0x00000030 /* R/W VME int 3 for LINT1 #define VINT_MAP0_LINT1_4 0x00000040 /* R/W VME int 4 for LINT1 #define VINT_MAP0_LINT1_5 0x00000050 /* R/W VME int 5 for LINT1 #define VINT_MAP0_LINT1_6 0x00000060 /* R/W VME int 6 for LINT1 #define VINT_MAP0_LINT1_7 0x00000070 /* R/W VME int 7 for LINT1 #define...
  • Page 160 VMICPCI-7715 Product Manual #define VINT_MAP1_DMA_6 0x00000006 /* R/W VME int 6 for DMA #define VINT_MAP1_DMA_7 0x00000007 /* R/W VME int 7 for DMA /* statid - interrupt STATUS/ID OUT 0x00XXXXXX */ #define STATID 0xFF000000 /* R/W interrupt status/ID out MASK...
  • Page 161 Directory CPU #define LINT_MAP2_LM0_6 0x00060000 /* R/W PCI int LINT#6 for LOC_MON0 */ #define LINT_MAP2_LM0_7 0x00070000 /* R/W PCI int LINT#7 for LOC_MON0 */ #define LINT_MAP2_MB3_0 0x00000000 /* R/W PCI int LINT#0 for MAILBOX3 */ #define LINT_MAP2_MB3_1 0x00001000 /* R/W PCI int LINT#1 for MAILBOX3 */ #define LINT_MAP2_MB3_2 0x00002000 /* R/W PCI int LINT#2 for MAILBOX3 */...
  • Page 162 VMICPCI-7715 Product Manual #define VINT_MAP2_MB2_3 0x00000300 /* R/W VME int VIRQ#3 for MAILBOX2 */ #define VINT_MAP2_MB2_4 0x00000400 /* R/W VME int VIRQ#4 for MAILBOX2 */ #define VINT_MAP2_MB2_5 0x00000500 /* R/W VME int VIRQ#5 for MAILBOX2 */ #define VINT_MAP2_MB2_6 0x00000600 /* R/W VME int VIRQ#6 for MAILBOX2 */...
  • Page 163 Directory CPU #define MAST_CTL_VREL_R 0x00100000 /* R/W VMEbus request mode ROR #define MAST_CTL_VREL_D 0x00000000 /* R/W VMEbus request mode RWD #define MAST_CTL_VOWN_R 0x00000000 /* W VMEbus ownership release #define MAST_CTL_VOWN_H 0x00080000 /* W VMEbus ownership hold #define MAST_CTL_VOWN_ACK 0x00040000 /* R VMEbus ownership due to hold #define MAST_CTL_PABS_32 0x00000000...
  • Page 164 VMICPCI-7715 Product Manual #define VSI_CTL_PWEN 0x40000000 /* R/W posted write enable #define VSI_CTL_PREN 0x20000000 /* R/W prefetch read enable #define VSI_CTL_AM_D 0x00400000 /* R/W AM code - data #define VSI_CTL_AM_P 0x00800000 /* R/W AM code - program #define VSI_CTL_AM_DP 0x00C00000 /* R/W AM code - both data &...
  • Page 165 Directory CPU #define LM_CTL_AM_SU 0x00300000 /* R/W location monitor AM = BOTH #define LM_CTL_AM_16 0x00000000 /* R/W location monitor AM = A16 #define LM_CTL_AM_24 0x00010000 /* R/W location monitor AM = A24 #define LM_CTL_AM_32 0x00020000 /* R/W location monitor AM = A32 /* vrai_ctl - VMEbus register access image control register */ #define VRAI_CTL_EN...

  • Page 166: Directory Smbus

    VMICPCI-7715 Product Manual Directory Smbus FILE: Pci.h define TRUE #define FALSE #define CARRY_FLAG 0x01 /* PCI Functions */ #define PCI_FUNCTION_ID 0xB1 #define PCI_BIOS_PRESENT 0x01 #define FIND_PCI_DEVICE 0x02 #define FIND_PCI_CLASS_CODE 0x03 #define READ_CONFIG_BYTE 0x08 #define READ_CONFIG_WORD 0x09 #define READ_CONFIG_DWORD 0x0A #define WRITE_CONFIG_BYTE...
  • Page 167 Directory Smbus /* Prototypes */ int find_pci_device(unsigned short device_id, unsigned short vendor_id, unsigned short index, unsigned char *bus_number, unsigned char *device_and_function); int read_configuration_area(unsigned char function, unsigned char bus_number, unsigned char device_and_function, unsigned char register_number, unsigned long *data); int write_configuration_area(unsigned char function, unsigned char bus_number, unsigned char device_and_function, unsigned char register_number,...

  • Page 168: File: Scan.h

    VMICPCI-7715 Product Manual ** FILE: SCAN.H #define SMBHSTSTS 0x00 /* SMBus host status register */ #define SMBSLVSTS 0x01 /* SMBus slave status register */ #define SMBHSTCNT 0x02 /* SMBus host control register */ #define SMBHSTCMD 0x03 /* SMBus host command register */...

  • Page 169: Directory Sram

    Directory SRAM Directory SRAM **File: T_SRAM.C /****************************************************************************/ /* FILE: T_SRAM.C /* Test battery backed SRAM with patterns and data=address. /****************************************************************************/ #include <stdlib.h> #include <stdio.h> #include <dos.h> unsigned char far * b_ptr; unsigned int far * w_ptr; unsigned long far * l_ptr; unsigned int far * buf_ptr;...
  • Page 170 VMICPCI-7715 Product Manual bdat = (unsigned char) pat[x]; for( i = 0x18; i < 0x8000; i++ ) { brd = *b_ptr++; if( bdat != brd ) { printf("FAILED\nBYTE DATA @ ADDR: %Fp WR: %.2X RD: %.2X\n", --b_ptr, bdat, brd );...
  • Page 171 Directory SRAM printf("FAILED\nLONG DATA @ ADDR: %Fp WR: %.8X RD: %.8X\n", --l_ptr, ldat, lrd ); exit( 1 ); ldat = ~ldat; /* fill and test buf with DATA = ADD LONG */ for( x = 0; x < 4; x++ ) { l_ptr = (unsigned long far *) MK_FP( 0xD800, 0x18 );...

  • Page 172: Directory Timers

    This directory contains sample code useful in the creation of applications involving the VMICPCI-7715’s three software controlled 16-bit timers. The code is written for the control of a single timer, but can be utilized in generating code for any timer configuration.
  • Page 173 Directory Timers #define CW_RB_CNT 0x00 /* W Read back count #define CW_RB_STAT 0x00 /* W Read back status #define CW_RB_C0 0x02 /* W Read back counter 0 #define CW_RB_C1 0x04 /* W Read back counter 1 #define CW_RB_C2 0x08 /* W Read back counter 2...

  • Page 174: File: Pci.h

    VMICPCI-7715 Product Manual **File: PCI.H define TRUE #define FALSE 0 #define CARRY_FLAG 0x01 /* PCI Functions */ #define PCI_FUNCTION_ID 0xB1 #define PCI_BIOS_PRESENT 0x01 #define FIND_PCI_DEVICE 0x02 #define FIND_PCI_CLASS_CODE 0x03 #define READ_CONFIG_BYTE 0x08 #define READ_CONFIG_WORD 0x09 #define READ_CONFIG_DWORD 0x0A #define WRITE_CONFIG_BYTE...
  • Page 175 Directory Timers unsigned short index, unsigned char *bus_number, unsigned char *device_and_function); int read_configuration_area(unsigned char function, unsigned char bus_number, unsigned char device_and_function, unsigned char register_number, unsigned long *data); int write_configuration_area(unsigned char function, unsigned char bus_number, unsigned char device_and_function, unsigned char register_number, unsigned long value);...

  • Page 176: File: Pci.c

    VMICPCI-7715 Product Manual **File: PCI.C #include <dos.h> #include <stddef.h> #include "pci.h" #define HIGH_BYTE(ax) (ax >> 8) #define LOW_BYTE(ax) (ax & 0xff) int find_pci_device(unsigned short device_id, unsigned short vendor_id, unsigned short index, unsigned char *bus_number, unsigned char *device_and_function) int ret_status; unsigned short ax, bx, flags;...
  • Page 177 Directory Timers int read_configuration_area(unsigned char function, unsigned char bus_number, unsigned char device_and_function, unsigned char register_number, unsigned long *data) int ret_status; unsigned short ax, flags; unsigned long ecx; _BH = bus_number; _BL = device_and_function; _DI = register_number; _AH = PCI_FUNCTION_ID; _AL = function; geninterrupt(0x1a);...
  • Page 178 VMICPCI-7715 Product Manual _BH = bus_number; _BL = device_and_function; _ECX = value; _DI = register_number; _AH = PCI_FUNCTION_ID; _AL = function; geninterrupt(0x1a); ax = _AX; flags = _FLAGS; if ((flags & CARRY_FLAG) == 0) ret_status = HIGH_BYTE(ax); else ret_status = NOT_SUCCESSFUL;...

  • Page 179: File: T_Timers.c

    Directory Timers **File: T_Timers.C *****************************************************************************/ FILE: T_TIMERS.C Test Timers (TIC is jumper selectable for 500 ns or 1 us) /****************************************************************************/ #include <stdlib.h> #include <stdio.h> #include <string.h> #include <conio.h> #include <ctype.h> #include <dos.h> #include "pci.h" #include "cpu.h" /* TT.C function prototypes */ void do_exit( int );...
  • Page 180 VMICPCI-7715 Product Manual /* try to locate the power management device on the PCI bus */ test_int = find_pci_device(DID_PWR_MGM, VID_PWR_MGM, 0, &bus, &dev_func); if(test_int != SUCCESSFUL) printf("\nUnable to locate power management device on PCI bus\n"); do_exit( 1 ); /* get base address from config area */ test_int = read_configuration_area(READ_CONFIG_DWORD, bus, dev_func, 0x40, &temp_dword);...
  • Page 181 Directory Timers test_int = 100; /* load counters */ load_counter( 1, 0xFFFF ); if( t1_count ) { t1++; break; test_int--; delay( 1 ); } while( test_int ); outp( timer_base + TIMER_CNTL, (CW_SC0 | CW_LSBMSB | CW_M2) ); outp( timer_base + TIMER_CNTL, (CW_SC1 | CW_LSBMSB | CW_M2) ); outp( timer_base + TIMER_CNTL, (CW_SC2 | CW_LSBMSB | CW_M2) );...
  • Page 182 VMICPCI-7715 Product Manual outp( gpo_base, ( gpo_org & GPO_CLR ) ); /* set all three GPO outputs to 1 to allow int status registers to function */ outp( gpo_base, ( gpo_org | GPO_T1 | GPO_T2 | GPO_T3 ) ); if( t1 && t2 && t3 ) printf("PASSED\n");...

  • Page 183: File: Timer.c

    Directory Timers **File: Timer.C FILE: TIMERS.C #include <stdlib.h> #include <stdio.h> #include <dos.h> #include <ctype.h> #include <conio.h> #include "cpu.h" /* function prototypes */ void far interrupt irq_rcvd( void ); void init_timer_int( void ); void restore_orig_int( void ); void load_counter( int, unsigned int ); void read_counter( int, unsigned int *, unsigned char * );...
  • Page 184 VMICPCI-7715 Product Manual void init_timer_int( void ) disable(); old_vect = getvect( IRQ5 ); /* save vector for IRQ5 */ setvect( IRQ5, irq_rcvd ); /* enable interrupt 5 */ outp(0x21, (pic1_org & 0xDF) ); /* 0 = enable 1 = disable */ /* clear all three GPO inputs */ outp( gpo_base, ( gpo_org &...
  • Page 185 Directory Timers /*******************************************************************/ return value: none /*******************************************************************/ void load_counter( int counter, unsigned int count ) int lsb, msb; lsb = count & 0xff; msb = count >> 8; switch( counter ) case 1: /* select counter 1, LSB then MSB, mode 2 */ outp( timer_base + TIMER_CNTL, (CW_SC0 | CW_LSBMSB | CW_M2) );...
  • Page 186 VMICPCI-7715 Product Manual int lsb, msb; switch( counter ) case 1: /* select counter 1, LSB then MSB */ outp( timer_base + TIMER_CNTL, ( CW_RBC | CW_RB_CNT | CW_RB_STAT | CW_RB_C0 ) *status = inp( timer_base + TIMER_CNTR1 ) & 0xFF;...
  • Page 187 Directory Timers disable(); asm { .386P push push tmr_status = inp( gpi_base ) & 0xFF; /* increment counts and clear status */ if( tmr_status & GPI_T1 ) { t1_count++; outp( gpo_base, (gpo_org & (~GPO_T1)) ); /* clear timer 1 status bit */ if( tmr_status &...

  • Page 188: Directory Watchdog

    VMICPCI-7715 Product Manual Directory WATCHDOG This directory contains sample code useful in the creation of applications involving the VMICPCI-7715’s watchdog timer function as described in Chapter 4. **File: Watchdog.H ** DS1384 REGISTER OFFSETS /* 7 #define CLK_MSEC 0x00 /* 00-99...

  • Page 189: File: Wdt0_Rst.c

    Directory WATCHDOG **File: WDT0_RST.C /****************************************************************************/ /* FILE: WDTO_RST.C /* Setup watchdog to issue reset on time out. /****************************************************************************/ #include <stdlib.h> #include <stdio.h> #include <dos.h> #include <time.h> #include <conio.h> #include <ctype.h> #include "watchdog.h" unsigned char far * wd_ptr; time_t t; char usr[80]; char reg_b;...
  • Page 190 VMICPCI-7715 Product Manual...

  • Page 191: Index

    Index 100BaseTx 10BaseT 82C54 address space features port map address map installation auxiliary I/O mapping Intels 21143 internal timer/counter BIOS interrupt line assignment BIOS setup screens interrupt vector table block diagram ISA bus ISA device interrupt mapping CMOS configuration ISA devices Configuring the DiskOnChip Control Word Register LPT1 Parallel I/O...
  • Page 192 VMICPCI-7715 Product Manual PCI IDE controller PCI ISA bridge PCI Mezzanine Card (PMC) PIIX4 82371EB Power-on Self Test programmable timer protected mode Read-Back Command real mode real-time clock refresh rates resister locations Return Material Authorization (RMA) number screen resolutions Select Timer Serial I/O (COM1,2,3 &...

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