1. Manuals
  2. Brands
  3. VMIC Manuals
  4. Motherboard
  5. VMIVME-7697
  6. Product manual

VMIC VMIVME-7697 Product Manual

Pentium iii processor-based vmebus cpu
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
VMIC VMIVME-7697 Product Manual

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the VMIVME-7697 and is the answer not in the manual?

Questions and answers

Related Manuals for VMIC VMIVME-7697

Summary of Contents for VMIC VMIVME-7697

  • Page 1 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...
  • Page 2 VMIVME-7697 ® Pentium III Processor-Based VMEbus CPU Product Manual 12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA 500-007697-000 Rev. B (256) 880-0444 (800) 322-3616 Fax: (256) 882-0859 7-Feb-2000 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 3 12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA (256) 880-0444 (800) 322-3616 Fax: (256) 882-0859 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 4 VMIC reserves the right to make any changes, without notice, to this or any of VMIC’s products to improve reliability, performance, function, or design. VMIC does not assume any liability arising out of the application or use of any product or circuit described herein; nor does VMIC convey any license under its patent rights or the rights of others.
  • Page 5 12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA (256) 880-0444 (800) 322-3616 Fax: (256) 882-0859 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 6: Table Of Contents

    VMIVME-7697 Product Options ........
  • Page 7 VMIVME-7697 Product Manual PCI Interrupts ................
  • Page 8 Table of Contents Video Connector Pinout ..............Parallel Port Connector Pinout .
  • Page 9 VMIVME-7697 Product Manual Boot Sequence ............... . .
  • Page 10 Table of Contents Doze Mode ................Standby Mode .
  • Page 11 VMIVME-7697 Product Manual BIOS Features Setup ...............
  • Page 12 Table of Contents ISA Devices ................PCI Devices .
  • Page 13 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 14 VMIVME-7697 VMEbus Functions ..........29 Figure 2-1 VMIVME-7697 CPU Board, I/O Port, and Jumper Locations ..... . . 33 Figure 2-2 VMIVME-7697 Top Board Jumper and Connector Locations .
  • Page 15 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 16 VMIVME-7697 Top Board Connectors ........
  • Page 17 VMIVME-7697 Product Manual Table 4-12 Timer Enable/Interrupt (TEI) Register: Offset 34h ......Table 4-13 Timer Interrupt Status (TIS) Register, Offset 38h ......

  • Page 18: Chapter 1 - Overview

    VMEbus modules via the on-board PCI-to-VMEbus bridge and the Endian conversion hardware. The VMIVME-7697 may be accessed as a VMEbus slave board. The VMEbus functions are available by programming the VMIVME-7697’s PCI-to-VMEbus bridge according to the references defined in this volume and/or in the second volume dedicated to the optional PCI-to-VMEbus interface board titled: VMIVME-7697 Tundra Universe -Based VMEbus Interface Product Manual (document No.

  • Page 19: Organization Of The Manual

    Organization of the Manual This manual is composed of the following chapters and appendices: Chapter 1 - VMIVME-7697 Features and Options describes the features of the base unit followed by descriptions of the associated features of the unit in operation on a VMEbus.

  • Page 20: References

    References References For the most up-to-date specifications for the VMIVME-7697, please refer to: VMIC specification number 800-007697-000 The following books refer to the Tundra Universe II-based interface option available in the VMIVME-7697: VMIVME-7697, Tundra Universe II -Based VMEbus Interface ™...
  • Page 21 VMIVME-7697 Product Manual PCI Special Interest Group 2575 NE Kathryn St #17 Hillsboro, OR 97124 FAX: 503-693-8344 The VMEbus interrupt and control software library references included for Windows NT: VMISFT-9420 IOWorks Access User’s Guide Doc. No. 520-009420-910 VMIC 12090 South Memorial Parkway...

  • Page 22: Safety Summary

    Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of this product. VMIC assumes no liability for the customer’s failure to comply with these requirements. Ground the System To minimize shock hazard, the chassis and system cabinet must be connected to an electrical ground.

  • Page 23: Safety Symbols Used In This Manual

    VMIVME-7697 Product Manual Safety Symbols Used in This Manual Indicates dangerous voltage (terminals fed from the interior by voltage exceeding 1000 V are so marked). Protective conductor terminal. For protection against electrical shock in case of a fault. Used with field wiring terminals to indicate the terminal which must be connected to ground before operating equipment.

  • Page 24: Notation And Terminology

    Notation and Terminology Notation and Terminology This product bridges the traditionally divergent worlds of Intel-based PC’s and Motorola-based VMEbus controllers; therefore, some confusion over “conventional” notation and terminology may exist. Every effort has been made to make this manual consistent by adhering to conventions typical for the Motorola/VMEbus world; nevertheless, users in both camps should review the following notes: •...
  • Page 25 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 26: Chapter 2 - Vmivme-7697 Features And Options

    VMIVME-7697 Product Options ........

  • Page 27: Table 1-1 Pc/At I/O Features

    VMIVME-7697 Product Manual The VMIVME-7697 supports standard PC/AT I/O features such as those listed in Table 1-1. Figure 1-1 on page 27 shows a block diagram of the VMIVME-7697 emphasizing the I/O features, including the PCI-to-VMEbus bridge. Table 1-1 PC/AT I/O Features...

  • Page 28: Figure 1-1 Vmivme-7697 Block Diagram

    128 Kbyte PCI-to-EIDE with NVRAM Parallel Port Flash BIOS Watchdog Timer Hard NVRAM Controller DS1384 Floppy Drive Drive FDC37C67X PS/2 Keyboard PS/2 Mouse Figure 1-1 VMIVME-7697 Block Diagram Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 29: Vmebus Features

    VMIVME-7697 Product Manual VMEbus Features In addition to its PC/AT functions, the VMIVME-7697 has the following VMEbus features: • Dual-slot, 6U height VMEbus board • Complete six-line Address Modifier (AM-Code) programmability • VME data interface with separate hardware byte/word swapping for master and slave accesses •...

  • Page 30: Vmivme-7697 Product Options

    These options are subject to change based on emerging technologies and availability of vendor configurations. The options and current details available with the VMIVME-7697 are defined in the device specification sheet available from your VMIC representative. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 31 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 32: Chapter 3 - Installation And Setup

    All claims arising from shipping damage should be filed with the carrier and a complete report sent to VMIC Customer Service together with a request for advice concerning the disposition of the damaged item(s).

  • Page 33: Hardware Setup

    In order to gain access to these five jumpers (on Rev A boards) the user may have to remove the VMIVME-7697 front panel. If required please follow the steps below to remove the front panel.

  • Page 34: Figure 2-1 Vmivme-7697 Cpu Board, I/O Port, And Jumper Locations

    (Not Shown) Parallel Port (Not Shown) COM 1 Ethernet Status Indicator SVGA Port 10BaseT/ 100 Base Tx Figure 2-1 VMIVME-7697 CPU Board, I/O Port, and Jumper Locations Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 35: Table 2-1 Vmivme-7697 Board Connectors

    VMIVME-7697 Product Manual Table 2-1 VMIVME-7697 Board Connectors Connector Function ITP Connectors Port 80 Connector Ethernet Connector Video Connector Board to Board Connector PS/2 Keyboard Connector PS/2 Mouse Connector VME Connector VME Connector SO DIMM Connector Parallel Port Connector USB Connector...

  • Page 36: Table 2-3 Clear Cmos - Jumper (E3)

    Hardware Setup The VMIVME-7697’s BIOS has the capability (Default: Disabled) of password Note protecting casual access to the unit’s CMOS set-up screens. The Password Clear jumper (E3) allows for a means to clear the password feature, as might be necessary to do in the case of a forgotten password.

  • Page 37: Table 2-6 Vmebus System Reset Receiver - Jumper (E7)

    VMIVME-7697 Product Manual Table 2-6 VMEbus System Reset Receiver - Jumper (E7) Select Jumper Position Active Disabled Table 2-7 VMEbus SYSFAIL On Reset - Jumper (E8) Select Jumper Position Active Disabled Table 2-8 Universe II MEM/IO Map - Jumper (E9)

  • Page 38: Table 2-11 Cmos Battery Enable - Jumper (E16)

    Hardware Setup Table 2-11 CMOS Battery Enable - Jumper (E16) Jumper Position CMOS Battery Disabled CMOS Battery Enabled Table 2-12 Watchdog Reset - Jumper (E18) Select Jumper Position Active Disabled Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 39: Figure 2-2 Vmivme-7697 Top Board Jumper And Connector Locations

    VMIVME-7697 Product Manual Figure 2-2 VMIVME-7697 Top Board Jumper and Connector Locations Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 40: Table 2-13 Vmivme-7697 Top Board Connectors

    Hardware Setup The following connectors and jumpers are found on the VMIVME-7697 top board. Default settings are in bold type. Table 2-13 VMIVME-7697 Top Board Connectors Connector Function J1 - J2 PMC Connectors P1 - P2 VME Connectors Board-to-Board Connector...

  • Page 41: Installation

    P1/P2 VMEbus backplane. If the VMIVME-7697 is to be the VMEbus system controller, choose the first two VMEbus slots. If some other board is the VMEbus system controller, choose any slot except slot one. The VMIVME-7697 does not require jumpers for enabling/disabling the system controller function.

  • Page 42: Bios Setup

    The CMOS configuration controls many details concerning the behavior of the hardware from the moment power is applied. The VMIVME-7697 is shipped from the factory with no hard drives configured in CMOS. The BIOS Setup program must be run to configure the specific drives attached.

  • Page 43: Led Definition

    VMIVME-7697 Product Manual LED Definition LED 1 Power - Indicates when power is applied to the board. VMIVME LED 2 Hard Drive Indicator - Indicates 7697 when hard drive activity is occurring. LED 3 SYSFAIL - Indicates when a VMEbus SYSFAIL is asserted.

  • Page 44: Chapter 4 - Pc/At Functions

    Furthermore, the VMIVME-7697 includes a PCI-compatible video adapter and Ethernet controller. The following sections describe in detail the PC/AT functions of the VMIVME-7697. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 45: Cpu Socket

    VMIVME-7697 Product Manual CPU Socket The VMIVME-7697 CPU socket is factory populated with a high-speed Pentium III processor. The CPU speed, SDRAM size and Compact Flash size are user-specified as part of the VMIVME-7697 ordering information. The options are not user-upgradable.

  • Page 46: Memory And Port Maps

    Memory and Port Maps Memory and Port Maps Memory Map - Tundra Universe II-Based PCI-to-VMEbus Bridge The memory map for the Tundra Universe II-based interface VMIVME-7697 is shown Table 3-1. All systems share this same memory map, although a VMIVME-7697 with less than the full 256 Mbyte of SDRAM does not fill the entire space reserved for On-Board Extended Memory.

  • Page 47: I/O Port Map

    The BIOS initializes and configures all these registers properly; adjusting these I/O ports directly is not normally necessary. The assigned and user-available I/O addresses are summarized in the I/O Address Map, Table 3-2. Table 3-2 VMIVME-7697 I/O Address Map I/O ADDRESS SIZE IN HW DEVICE PC/AT FUNCTION RANGE...
  • Page 48 Reserved * While these I/O ports are reserved for the listed functions, they are not implemented on the VMIVME-7697. They are listed here to make the user aware of the standard PC/AT usage of these ports. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 49: Pc/At Interrupts

    Table 3-4. The interrupt hardware implementation on the VMIVME-7697 is standard for computers built around the PC/AT architecture, which evolved from the IBM PC/XT. In the IBM PC/XT computers, only eight interrupt request lines exist, numbered from IRQ0 to IRQ7 at the PIC.

  • Page 50: Table 3-4 Pc/At Interrupt Vector Table

    PC/AT Interrupts Table 3-3 PC/AT Hardware Interrupt Line Assignments AT FUNCTION COMMENTS Not Assigned Determined by BIOS Not Assigned Determined by BIOS Mouse Math Coprocessor AT Hard Drive Flash Drive Table 3-4 PC/AT Interrupt Vector Table INTERRUPT NO. REAL MODE PROTECTED MODE LINE Divide Error...
  • Page 51 VMIVME-7697 Product Manual Table 3-4 PC/AT Interrupt Vector Table (Continued) INTERRUPT NO. REAL MODE PROTECTED MODE LINE BIOS Video I/O Coprocessor Error Eqpt Configuration Check Same as Real Mode Memory Size Check Same as Real Mode XT Floppy/Hard Drive Same as Real Mode...
  • Page 52 PC/AT Interrupts Table 3-4 PC/AT Interrupt Vector Table (Continued) INTERRUPT NO. REAL MODE PROTECTED MODE LINE DOS 3.x+ Network Comm Same as Real Mode DOS Internal Use Same as Real Mode DOS Internal Use Same as Real Mode DOS Internal Use Same as Real Mode DOS Internal Use Same as Real Mode...

  • Page 53: Pci Interrupts

    Figure 3-1 on page 54 depicts the VMIVME-7697 interrupt logic pertaining to VMEbus operations and the PCI expansion site. Any function on a multifunction device can be connected to any of the INTx# lines.

  • Page 54: I/O Ports

    NMI Enable - 1 = Disable, 0 = Enable I/O Ports The VMIVME-7697 incorporates the SMC Super-I/O chip. The SMC chip provides the VMIVME-7697 with a standard floppy drive controller, two 16550 UART-compatible serial ports, and one standard DB25 parallel port. The Ultra-IDE hard drive interface is provided by the Intel 82371EB (PIIX4E) PCI ISA IDE Xcelerator chip.

  • Page 55: Figure 3-1 Connections For The Pc Interrupt Logic Controller

    VMIVME-7697 Product Manual INTR 8259 MASTER-PORTS $020-$021 Interrupt Com 2 Floppy Timer Keybd Com 1 Timer Lpt 1 8-15 Control IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 8259 SLAVE- PORTS $0A0-$0A1 Real-Tm IRQ2 Mouse Math Flash Hard Drv Drive...

  • Page 56: Video Graphics Adapter

    Video Graphics Adapter Video Graphics Adapter The monitor port on the VMIVME-7697 is controlled by a S3 Trio 3d AGP chip with 4 Mbyte video DRAM. The video controller chip is hardware and BIOS compatible with the IBM EGA and SVGA standards and also supports VESA high-resolution and extended video modes.

  • Page 57: Ethernet Controller

    10BaseT has a theoretical maximum length of 100 m from the wiring hub to the terminal node. 100BaseTx The VMIVME-7697 also supports the 100BaseTx Ethernet. A network based on a 100BaseTx standard uses unshielded twisted-pair cables and a RJ-45 connector. The 100BaseTx has a theoretical maximum deployment length of 250 m.

  • Page 58: Universal Serial Bus

    The cable from the external devices attaches to the VMIVME-7697 at the VMEbus P2 connector. The SCSI connector and pinout is shown in Appendix A. For best overall reliability, it is suggested that total cable length should not exceed 3 meters for SCSI2 Fast devices and 1.5 meters for...
  • Page 59 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 60: Chapter 5 - Embedded Pc/Rtos Features

    Watchdog Timer for synchronizing and controlling multiple events in embedded applications. The VMIVME-7697 also provides a bootable flash disk system, and 128 K byte of nonvolatile, battery-backed SRAM. These features make the unit ideal for embedded applications, particularly applications where standard hard drives and floppy disk drives cannot be used.

  • Page 61: Timers

    The use of software alone to generate timing loops is awkward and wastes processor cycles. The hardware timers on-board the VMIVME-7697 are designed to offload from software the task of generating timing loops. Instead of generating software loops, the software engineer can configure each of the VMIVME-7697 timers to generate a periodic interrupt.

  • Page 62: Timer Functionality

    Timers The Timer Control section is the core of the Timer Structure. It contains the Timer Control circuitry, the Interrupt Status Block, and the Timer Control Registers. The Timer Control circuitry manages each timer and signals the Interrupt Control Block when a timer has timed out.

  • Page 63: Figure 4-1 Vmivme-7697 Timer Block Diagram

    Timer 2 Control Local CPU Bus Figure 4-1 VMIVME-7697 Timer Block Diagram The timers are set up by default to be 32 bits wide, but must be set to 16 bits wide for a time period of 65,538 µs or less. The Counter Value is loaded by first writing a Timer...

  • Page 64: Table 4-2 Counter Value/Cycle Time Range Table (X Is Counter Value)

    Timers At the end of the programmed time interval, the timer signals the Timer Control circuitry. The Timer Control circuitry sets a bit in the Timer Interrupt Status (TIS) register (reference Table 4-12 on page 73). The Timer Control circuitry then reinitializes the time to the original counter value and the timer starts counting again.

  • Page 65: Polling

    Polling The VMIVME-7697 Timers can be used as polled timers. Two incidental characteristics of the timers must be kept in mind while polling. First, the timers, when counting in 16 or 32 bit mode, will always transition through an all 0xF state immediately prior to reinitialzation.

  • Page 66: Timer Status

    131392 0x0002013F VMIC recommends that a value of one (1) be added to the polled value to obtain the correct count removing the all 0xF state. The 16 bit example with one (1) added to the polled value would be as follows:...

  • Page 67: Timer Read-Back

    VMIVME-7697 Product Manual The Timer Interrupt/Status register is used to clear timer interrupts as well as to determine timer rollover when interrupts are not being used. The Interrupt/Status bits are set when a timer has rolled over. If the specific timer is set up to cause interrupts, the action of the bit being set causes an interrupt.

  • Page 68: Table 4-5 16-Bit Read/Mode Command Example

    Timers Table 4-5 shows an example sequence of reading the 32-bit count from Timer 1 set in Table 4-5 16-bit Read/Mode Command Example Address Data Step offset Description (HEX) (HEX) Write Read-Back command to Timer 0’s TMR Register Read the LSB of Lower Counter Read the MSB of Lower Counter 32-bit mode.

  • Page 69: Timer Control Registers

    A detailed description of the programming of these registers follows. Programming Upon powerup of the VMIVME-7697, the timers are in an undefined state. Each timer must be set up and enabled before it can be used. Each timer is completely independent of the others.

  • Page 70: Table 4-7 Timer Section Address Map

    Timer Control Registers Table 4-7 Timer Section Address Map Address Offset Segment Description AD[5...0] Timer 0 Scale Counter (SC0) Timer 0 Lower Counter (LC0) Timer 0 Upper Counter (UC0) Timer 0 Timer Mode Register (TMR0) Timer 1 Scale Counter (SC1) Timer 1 Lower Counter (LC1) Timer 1...

  • Page 71: Timer Width Control/System State (Twss) Register, Offset 30H

    VMIVME-7697 Product Manual The timer width is controlled by the Timer Width Bit Field (bits 2 to 0) of the Timer Width/System State (TWSS) Register (see Table 4-8). This register is located at offset 0x30 from the Timer PCI memory base address. Each of the bits correspond to one of the three timers.

  • Page 72: Table 4-9 Timer Mode Register Values

    Timer Control Registers Before each individual Counter is loaded with its Counter Value, a unique counter-specific control byte must be written to the Timer Mode Register (TMRx). Table 4-9 shows the Timer Mode Bytes. More specifically, before a Counter Value is loaded into the Scale Counter, the Scale Timer Mode byte (36) must be written to the Timer Mode Register.

  • Page 73: Timer Enable/Interrupt (Tei) Register: Offset 34H

    VMIVME-7697 Product Manual Table 4-10 16-bit Wide Timer Counter Value Load Example Address Data Step Offset Description (HEX) (HEX) Timer Mode Register (TMR0) byte setting up the Lower Counter of Timer 0. LSB byte of the counter value written to LC0.

  • Page 74: Timer Interrupt Status (Tis) Register, Offset 38H

    Timer Control Registers Bits 2 to 0 of the Timer Enable/Interrupt (TEI) Register are the enable bits for each timer, respectively. Bit 0 enables Timer 0, Bit 1 enables Timer 1, etc. When the bit is set to zero (0), the timer is disabled. When the bit is set to a one (1), the timer is enabled. Table 4-12 Timer Enable/Interrupt (TEI) Register: Offset 34h Field Description...

  • Page 75: Watchdog Timer

    The Time of Day feature found within the DS1284 device is explained in this section, but is not utilized by the VMIVME-7697. The actual Time of Day registers used by the VMIVME-7697 are located at the standard PC/AT I/O address. The Time of Day feature in the DS1284 Watchdog Timer is available for use by the user at their discretion.

  • Page 76: Table 4-14 Watchdog Registers

    Watchdog Timer Table 4-14 Watchdog Registers Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Range Base + 0 0.1 Seconds (BCD) 0.01 Seconds (BCD) 00 - 99 Base + 1 10 Seconds (BCD) Seconds (BCD) 00 - 59...

  • Page 77: Time Of Day Registers

    VMIVME-7697 Product Manual periodically by the transfer of the incremented internal values. Registers 0, 1, 2, 4, 6, 8, 9, and A contain Time of Day and Data information in Binary Coded Decimal (BCD). Registers 3, 5, and 7 contain the Time of Day Alarm information in BCD. The Command Register (Register B) contains data in binary.

  • Page 78: Time Of Day Alarm Registers

    Watchdog Timer Register 9 contains two Time of Day values. Bits 3 - 0 contain the Months value with a range of 0 to 9 in BCD while Bits 4 contain the 10 Date value with a range of 0 to 1. This Register has a total range of 01 to 12.

  • Page 79: Watchdog Alarm Registers

    VMIVME-7697 Product Manual Table 4-15 Time of Day Alarm Registers Register Comment Minutes Hours Days Alarm once per minute Alarm when minutes match Alarm when hours and minutes match Alarm when hours, minutes, and days match The Time of Day Alarm registers are read and written to in the same format as the Time of Day registers.

  • Page 80: Watchdog Output Routing Register

    Watchdog Timer Ipsw - Bit 6 Interrupt Switch - This bit toggles the Interrupt Output between the Time of Day Alarm and the Watchdog Alarm. When set to a logic zero (0), the Interrupt Output is from the Watchdog Alarm. When set to a logic one (1), the Interrupt Output is from the Time of Day Alarm.

  • Page 81: Battery Backed Sram

    VMIVME-7697 Product Manual Battery Backed SRAM The VMIVME-7697 includes 128 K byte of battery-backed SRAM addressed in PCI memory space. Table 4-1 shows the PCI Base Address register (NVRAM, 1Ch) for the battery backed SRAM. The battery-backed SRAM can be accessed by the CPU at anytime, and can be used to store system data that must not be lost during power-off conditions.

  • Page 82: Flash Disk

    Configuration The flash disk resides on the VMIVME-7697 as the secondary IDE bus master device (the secondary IDE bus slave device is not assignable). The default setting in the AWARD ‘STANDARD CMOS SETUP’ screen is the ‘AUTO’ setting. In the AWARD ‘INTERGRATED PERIPHERAL’...

  • Page 83: Functionality

    Some applications may require the use of multiple partitions. The following discussion of partitions includes the special procedures that must be followed to allow the creation of multiple partitions on the VMIVME-7697 IDE disk devices (including the resident Flash Disk).
  • Page 84 FDISK. This has been shown to be an important step in a successful partitioning effort. 1. Power up the VMIVME-7697, and enter CMOS Set-up. 2. Set Primary Master to “Not Installed”. Set Secondary Master to “Auto”. 3. Set boot device to floppy.
  • Page 85 VMIVME-7697 Product Manual 17. Set boot device to desired boot source. Drive letter assignments for a simple system were illustrated in Figure 4-3. Understanding the order the operating system assigns drive letters is necessary for these multiple partition configurations. The operating system assigns drive letter C: to the active primary partition on the first hard disk (the boot device).

  • Page 86: Chapter 6 - Maintenance

    8. Quality of cables and I/O connections If products must be returned, contact VMIC for a Return Material Authorization (RMA) Number. This RMA Number must be obtained prior to any return. VMIC Customer Service is available at: 1-800-240-7782.
  • Page 87 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 88: Appendix A - Connector Pinouts

    I/O ports. Figure A-1 shows the locations of the connectors on the VMIVME-7697. Wherever possible, the VMIVME-7697 uses connectors and pinouts typical for any desktop PC. This ensures maximum compatibility with a variety of systems. Connector diagrams in this appendix are generally shown in a natural orientation with the controller board mounted in a VMEbus chassis.

  • Page 89: Figure A-1 Vmivme-7697 Connector Locations

    PWR Indicator Mouse Keyboard COM 2 (Not Shown) Parallel Port COM 1 (Not Shown) Ethernet Status Indicator SVGA Port 10BaseT/ 100 Base Tx Figure A-1 VMIVME-7697 Connector Locations Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 90: Ethernet Connector Pinout

    Ethernet Connector Pinout Ethernet Connector Pinout The pinout diagram for the Ethernet 10BaseT/100BaseTx connector is shown in Figure A-2. ETHERNET CONNECTOR 10BaseT/100BaseTx Signal Name Transmit Data Transmit Data Receive Data No Connection No Connection Receive Data 10BaseT/100BaseTx No Connection No Connection Figure A-2 Ethernet Connector Pinout Artisan Technology Group - Quality Instrumentation ...

  • Page 91: Figure A-3 Video Connector Pinout

    VMIVME-7697 Product Manual Video Connector Pinout The video port uses a standard high-density D15 SVGA connector. Figure A-3 illustrates the pinout. VIDEO CONNECTOR DIRECTION FUNCTION Green Blue Reserved Ground Ground Ground Ground Reserved Ground Reserved Reserved Horizontal Sync Vertical Sync...

  • Page 92: Figure A-4 Parallel Port Connector Pinout

    Parallel Port Connector Pinout Parallel Port Connector Pinout The parallel port shown in Figure A-4 uses a standard DB25 female connector typical of any PC/AT system. PARALLEL PORT CONNECTOR DIRECTION FUNCTION In/Out Data Strobe In/Out Bidirectional Data D0 In/Out Bidirectional Data D1 In/Out Bidirectional Data D2 In/Out...

  • Page 93: Figure A-5 Serial Connector Pinouts

    VMIVME-7697 Product Manual Serial Connector Pinout Each standard RS-232 serial port connector is a Microminiature D9 male as shown in the upper drawing in Figure A-5. Adapters to connect standard D9 serial peripherals to the board are available. Please refer to the product specification sheet for ordering information.

  • Page 94: Figure A-6 Keyboard Connector Pinout

    Keyboard Connector Pinout Keyboard Connector Pinout The keyboard connector is a standard 6-pin female mini-DIN PS/2 connector as shown in Figure A-6. KEYBOARD CONNECTOR FUNCTION In/Out Data Reserved Ground +5 V Clock Reserved Shield Chassis Ground Figure A-6 Keyboard Connector Pinout Artisan Technology Group - Quality Instrumentation ...

  • Page 95: Figure A-7 Mouse Connector Pinout

    VMIVME-7697 Product Manual Mouse Connector Pinout The mouse connector is a standard 6-pin female mini-DIN PS/2 connector as shown Figure A-7. MOUSE CONNECTOR FUNCTION In/Out Data Reserved Ground +5 V Clock Reserved Shield Chassis Ground Figure A-7 Mouse Connector Pinout...

  • Page 96: Figure A-8 Vmebus Connector Diagram

    VMEbus Connector Pinout VMEbus Connector Pinout Figure A-8 shows the location of the VMEbus P1 and P2 connectors and their orientation on the VMIVME-7697C (bottom board). Table A-1 shows the pin assignments for the VMEbus connectors. Note that only Row B of connector P2 is used;...
  • Page 97 VMIVME-7697 Product Manual Table A-1 VMEbus Connector Pinout (bottom board) (Continued) P1 ROW A P1 ROW B P1 ROW C P2 ROW A P2 ROW B P2 ROW C NUMBER SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL IDECS01 # DAP 0...

  • Page 98: Figure A-9 Vmebus Connector Diagram

    VMEbus Connector Pinout Figure A-9 shows the location of the VMEbus P1 and P2 connectors and their orientation on the VMIVME-7697I (top board). Table A-2 shows the pin assignments for the VMEbus connectors. Note that only Row B of connector P2 is used; all other pins on P2 are reserved and should not be connected.

  • Page 99: Table A-2 Vmebus Connector Pinout (Top Board)

    VMIVME-7697 Product Manual Table A-2 VMEbus Connector Pinout (top board) (Continued) P1 ROW A P1 ROW B P1 ROW C P2 ROW A P2 ROW B P2 ROW C NUMBER SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SSEL # SCD #...

  • Page 100: Usb Connector

    USB Connector USB Connector The USB port uses an industry standard 4 position shielded connector. Figure A-10 shows the pinout of the USB connector. End View Conductors USB CONNECTOR SIGNAL FUNCTION USBV USB Power USB- USB Data - USB+ USB Data + USBG USB Ground Figure A-10 USB Connector Pinout...
  • Page 101 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 102: Driver Software Installation

    Driver Software Installation In order to properly use the Video and LAN adapters of the VMIVME-7697, the user must install the driver software located on the distribution diskettes provided with the unit.

  • Page 103: Windows For Workgroups (Version 3.11)

    7. Again at the ‘NETWORK SETUP’ screen, click ‘CONTINUE’. 8. Under ‘ADD NETWORK ADAPTER’ click on ‘UNLISTED or UPDATED NETWORK ADAPTER’. Then click ‘OK’. 9. Insert the VMIVME-7697 distribution disk marked 320-500043-005 into drive A: and type: . Then click ‘OK’.
  • Page 104 Windows for Workgroups (Version 3.11) 16. Under the Windows setup screen select Options. Click on ‘Change System Setup’. 17. Click on the display line. Select ‘Other Display (requires Disk from OEM’. 18. In the Windows Setup window type then select ‘OK’. A:\32bit\ 19.

  • Page 105: Windows 95

    VMIVME-7697 Product Manual Windows 95 1. Format the hard drive with MS-DOS. 2. Begin installation of Windows 95, following the instructions provided by the Windows 95 manual. 3. When you reach the ‘WINDOWS 95 SETUP WIZARD SCREEN’, choose ‘TYPICAL’ under ‘SETUP OPTIONS’ and then click on ‘NEXT’.

  • Page 106: Scsi Driver Installation Directions For Windows 95

    Windows 95 21. At the ‘SYSTEM PROPERTIES’ window, click ‘OK’. 22. From ‘CONTROL PANEL’, double-click on the ‘NETWORK’ icon. 23. Under ‘NETWORK’, click on ‘FILE AND PRINT SHARING’ and choose the appropriate items for your system, click ‘OK’. 24. At the ‘NETWORK’ window, click ‘OK’. When prompted, insert the diskettes needed to complete the network installation, if required.

  • Page 107: Windows 95 Inf Update Utility For Intel(Tm) Chipsets

    VMIVME-7697 Product Manual Windows 95 INF Update Utility for Intel(TM) Chipsets This update allows the operating system to correctly identify the Intel(TM) chipset components and properly configure the system. 1. Windows 95 must be fully installed and running on the system prior to running this software.
  • Page 108 Windows 95 9. Select ’Yes’ when prompted to re-start Windows 95. After installation, the following driver and related files are stored as listed. • <Windows 95 directory>\SYSTEM\IOSUBSYS\IDEATAPI.MPD • <Windows 95 directory>\SYSTEM\IOSUBSYS\PIIXVSD.VXD • <Windows 95 directory>\INF\IDEATAPI.INF This driver is not to be used with Windows 98. The setup program must be rerun to Note uninstall the driver if Windows 98 is to be used.

  • Page 109: Windows Nt (Version 4.0)

    VMIVME-7697 Product Manual Windows NT (Version 4.0) Windows NT 4.0 includes drivers for the on-board LAN, and video adapters. The following steps are required to configure the LAN for operation. 1. Follow the normal Windows NT 4.0 installation until you reach the ‘WINDOWS NT WORKSTATION SETUP’...
  • Page 110 Windows NT (Version 4.0) 17. When the computer reboots, double-click on ‘MY COMPUTER’ window. 18. Double-click on the ‘CONTROL PANEL’ icon in the ‘MY COMPUTER’ window. 19. Double-click on the ‘DISPLAY’ icon in the ‘CONTROL PANEL’. 20. Select the ‘SETTINGS’ tab in the ‘DISPLAY PROPERTIES’ window, then click on the ‘DISPLAY TYPE’...
  • Page 111 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 112 Integrated Peripherals ..........128 Introduction The VMIVME-7697 utilizes the BIOS (Basic Input/Output system) in the same manner as other PC/AT compatible computers. This appendix describes the menus and options associated with the VMIVME-7697 BIOS.

  • Page 113: System Bios Setup Utility

    VMIVME-7697 Product Manual System BIOS Setup Utility During system bootup, press the Delete key to access the Award EliteBIOS CMOS Setup Utility screen. From this screen, the user can select any section of the Award (system) BIOS for configuration, such as floppy drive configuration or system memory.

  • Page 114: Standard Cmos Setup

    Press the PgUp or PgDn key to step through the available choices, or type in the information. Primary Master/Slave The VMIVME-7697 has the capability of utilizing one IDE hard disk drive on the Primary Master bus. The default setting is None. The Primary Slave is not used with the VMIVME-7697.

  • Page 115: Secondary Master/Slave

    Use PgUp or Pgdn to select the floppy drive. The default is 1.44M, 3.5 inch. Floppy Drive B The VMIVME-7697 does not support a second floppy drive. The default is None. Video The VMIVME-7697 has an EGA/VGA graphics chip onboard. The BIOS supports a secondary video subsystem, but it is not selected in Setup.

  • Page 116: Memory

    Standard CMOS Setup Memory The Memory field at the lower right of the screen is for informational purposes only and can not be modified by the user. This field displays the total RAM installed in the system, and the amounts allocated to base, extended, and other (high) memory. Artisan Technology Group - Quality Instrumentation ...

  • Page 117: Bios Features Setup

    VMIVME-7697 Product Manual BIOS Features Setup This screen, selected from the CMOS Setup Utility screen, allows the user to configure options that are in addition to the basic BIOS features. SPHÃQ8DDT6Ã7DPT 7DPTÃA@6UVS@TÃT@UVQ 6X6S9ÃTPAUX6S@ÃDI8 Wv…ˆ†ÃXh…vt ) 9v†hiyrq Srƒ‚…‡ÃI‚ÃA99ÃA‚…ÃXDI($) I‚ 8QVÃD‡r…hyÃ8hpur ) @hiyrq @‘‡r…hyÃ8hpur...

  • Page 118: Pentium Iii Serial Number

    (A:), then the internal hard drive (C:), followed by the SCSI drive. Swap Floppy Drive The option is functional only in a system with two floppy drives. The VMIVME-7697 supports only one floppy drive. Changing this option will have no effect on the system.

  • Page 119: Boot Up Numlock Status

    VMIVME-7697 Product Manual Boot Up NumLock Status Toggle between On or Off to control the state of the NumLock key when the system boots. When toggled On, the numeric keypad generates numbers instead of controlling the cursor operations. The default is Off.

  • Page 120: Os Select For Dram>64Mb

    BIOS Features Setup OS Select For DRAM>64MB Select OS2 only if you are running OS/2 operating system with greater than 64 MB of RAM on the system. The default is Non-OS2. HDD S.M.A.R.T. Capability SMART is an acronym for Self-Monitoring Analysis and Reporting Technology system.

  • Page 121: Chipset Features Setup

    VMIVME-7697 Product Manual Chipset Features Setup This section describes features of the Intel 82430TX PCIset. Advanced Options The parameters in this screen are for system designers, service personnel, and technically competent users only. Do not reset these values without a complete understanding of the consequences.

  • Page 122: Sdram Cas Latency Time

    Chipset Features Setup SDRAM CAS Latency Time When synchronous DRAM is installed, you can control the number of CLKs between when the SDRAMs sample a read command and when the controller samples read data from the SDRAMs. Do not reset this field from the default value specified by the system designer.

  • Page 123: Memory Hole At 15M-16M

    VMIVME-7697 Product Manual Memory Hole at 15M-16M This area of system memory may be reserved for ISA adapter ROM. When this area is reserved, it cannot be cached. Refer to the documentation that came with the peripheral that require the use of this area of system memory for memory requirements.

  • Page 124: Power Management

    Power Management Power Management This section discusses the power management features provided with the installed Award BIOS. SPHÃQ8DDT6Ã7DPT QPX@SÃH6I6B@H@IUÃT@UVQ 6X6S9ÃTPAUX6S@ÃDI8 68QDÃAˆp‡v‚ ) 9v†hiyrq ÃSry‚hqÃBy‚ihyÃUv€r…Ã@‰r‡†Ã Q‚r…ÃHhhtr€r‡ ) V†r…Ã9rsvrq DSRÃÃb"&( $dIHD ) 9v†hiyrq QHÃ8‚‡…‚yÃi’Ã6QH ) `r† Q…v€h…’ÃD9@à ) 9v†hiyrq Wvqr‚ÃPssÃHr‡u‚q ) WCÃT`I87yhx Q…v€h…’ÃD9@Ã...

  • Page 125: Pm Control By Apm

    VMIVME-7697 Product Manual PM Control by APM Advanced Power Management (APM) provides better power savings. The default is Video Off Method Determines the manner in which the monitor is blanked. The options are: • V/H SYNC+Blank System turns off vertical and horizontal synchronization ports and writes blanks to the video buffer.

  • Page 126: Throttle Duty Cycle

    Power Management Throttle Duty Cycle When the system enters Doze mode, the CPU clock runs only part of the time. You may select the percent of time that the clock runs. The default is 62.5%. VGA Active Monitor When Enabled, any video activity restarts the global timer for Standby mode. The default is Disabled.

  • Page 127: Pnp/Pci Configuration

    VMIVME-7697 Product Manual PnP/PCI Configuration This section describes the PNP/PCI options available. SPHÃQ8DDT6Ã7DPT QIQQ8DÃ8PIADBVS6UDPI 6X6S9ÃTPAUX6S@ÃDI8 QIQÃPTÃD†‡hyyrq ) I‚ V†rqÃH@HÃih†rÃhqq… ) I6 Sr†‚ˆ…pr†Ã8‚‡…‚yyrqÃ7’ ) Hhˆhy Sr†r‡Ã8‚svtˆ…h‡v‚Ã9h‡h ) 9v†hiyrq 6††vtÃDSRÃA‚…ÃVT7 ) 9v†hiyrq DSR"ÃÃÃh††vtrqÇ‚ ) Q8DDT6ÃQQ DSR#ÃÃÃh††vtrqÇ‚ ) Q8DDT6ÃQQ DSR$ÃÃÃh††vtrqÇ‚ ) Grthp’ÃDT6 DSR&ÃÃÃh††vtrqÇ‚...

  • Page 128: Irq N Assigned To

    PnP/PCI Configuration IRQ n Assigned to When resources are controlled manually, assign each system interrupt as one of the following types, depending on the type of device using the interrupt: • Legacy ISA Devices compliant with the original PC AT bus specification, requiring a specific interrupt (such as IRQ4 for serial port 1).

  • Page 129: Integrated Peripherals

    VMIVME-7697 Product Manual Integrated Peripherals This section describes the setup for integrated peripherals in the system. SPHÃQ8DDT6Ã7DPT DIU@BS6U@9ÃQ@SDQC@S6GT 6X6S9ÃTPAUX6S@ÃDI8 D9@ÃC99Ã7y‚pxÃH‚qr ) @hiyrq D9@ÃQ…v€h…’ÃHh†‡r…ÃQDP ) 6ˆ‡‚ Pi‚h…qÃQh…hyyryÃQ‚…‡ ) "&'DSR& D9@ÃQ…v€h…’ÃTyh‰rÃQDP ) 6ˆ‡‚ Qh…hyyryÃQ‚…‡ÃH‚qr ) I‚…€hy D9@ÃTrp‚qh…’ÃHh†‡r…ÃQDP ) 6ˆ‡‚ D9@ÃTrp‚qh…’ÃTyh‰rÃQDP ) 6ˆ‡‚...

  • Page 130: Ide Primary/Secondary Master Udma

    Integrated Peripherals IDE Primary/Secondary Master UDMA Ultra DMA/33 implementation is possible only if the IDE hard drive supports it and the operating environment includes a DMA driver (Windows 95 OSR2 or a third-party IDE bus master driver). If the hard drive and the operating system both support Ultra DMA/33, select Auto to enable BIOS support.

  • Page 131: Onboard Serial Port 1/2

    The default for both ports is Auto. UART 2 Mode Select an operating mode for the second serial port. The infrared options listed below are not supported by the VMIVME-7697. The options are: • Standard RS-232C serial port • IrDA 1.0 •...
  • Page 132 LANWorks BIOS Setup ..........134 Introduction The VMIVME-7697 includes the LANWorks option which allows the VMIVME-7697 to be booted from a network. This appendix describes the LANWorks BIOS Setup screen, and the procedures to enable this option.

  • Page 133: System Bios Setup Utility

    VMIVME-7697 Product Manual System BIOS Setup Utility To enable the LANWorks BIOS option reboot the VMIVME-7697 and when prompted, press the Delete key to access the System BIOS Setup Utility screen shown below. SPHÃQ8DDT6Ã7DPT 8HPTÃT@UVQÃVUDGDU` 6X6S9ÃTPAUX6S@ÃDI8 TU6I96S9Ã8HPTÃT@UVQ DIU@SBS6U@9ÃQ@SDQC@S6GT 7DPTÃA@6UVS@TÃT@UVQ TVQ@SWDTPSÃQ6TTXPS9 8CDQT@UÃA@6UVS@TÃT@UVQ...

  • Page 134: Bios Features Setup

    Using the arrow keys, enable Boot From LAN First. Exit the BIOS setup, saving changes. When prompted, press “Control-Alt-B” as the VMIVME-7697 reboots. This will activate the LANWorks BIOS setup screen. Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 135: Lanworks Bios Setup

    VMIVME-7697 Product Manual LANWorks BIOS Setup Below is the screen in which the various options for booting through LANWorks are set. 7‚‚‡Xh…rÃIr‡‚…xÃ7‚‚‡ÃSPH 8Ã8‚ƒ’…vtu‡ÃG6IX‚…x†ÃUrpu‚y‚tvr†ÃDpà ('& (('Ã6yyÃ…vtu‡†Ã…r†r…‰rq 98! #"Q8Dà  ÃW Ã(& "  18ˆ……r‡Ã†r‡ˆƒ3 1IrÃTr‡ˆƒ3 DPÃ7h†r) @#u DSR) 7‚‚‡ÃQ…‚‡‚p‚y) 9rshˆy‡Ã7‚‚‡) Ir‡‚…x Ir‡‚…x...
  • Page 136 The SCSI BIOS includes a configuration utility that enables users to change the VMIVME-7697 SCSI adapter settings. The utility lets users list the SCSI IDs of devices on the host adapter, format SCSI disk drives, and check drives for defects. This section describes the utility default and permitted settings, and the procedure for using the utility.
  • Page 137 VMIVME-7697 Product Manual AIC-7880 Ultra/Ultra W at Bus:Device 00:0Ah Would you like to configure the host adapter, or run the SCSI disk utilities? Select the option and press <Enter>. Press <F5> to switch between color and monochrome modes. Options Configure/View Host Adapter Settings SCSI Disk Utilities Artisan Technology Group - Quality Instrumentation ...

  • Page 138: Configure/View Host Adapter Settings

    Configure/View Host Adapter Settings Configure/View Host Adapter Settings Selection of the first main menu item, the Configure/View Host Adapter Settings, allows the user to adjust the SCSI Bus Interface Definitions. AIC-7880 Ultra/Ultra W at Bus:Device 00:0Ah Configuration SCSI Bus Interface Definitions Host Adapter SCSI ID ..........

  • Page 139: Scsi Bus Interface Definitions

    VMIVME-7697 Product Manual SCSI Bus Interface Definitions The SCSI bus Interface Definition default settings configure the unit for SCSI bus operation. The settings described here are for a host adapter SCSI ID, host adapter termination, and parity checking. Host Adapter SCSI ID Each device on the SCSI bus must have a unique SCSI ID.

  • Page 140: Additional Options

    Additional Options Additional Options Boot Device Options With the Boot Device options the user specifies the boot device. The default boot device is SCSI ID 0 and logical unit number (LUN) 0. To specify a different boot device, choose a different SCSI ID: ID 0 through 7 on 8-bit adapters, or ID 0 through 15 on 16-bit adapters.

  • Page 141: Initiate Sync Negotiation

    VMIVME-7697 Product Manual SCSI Device Configuration SCSI Device ID Initiate Sync Negotiation .... Maximum Sync Transfer Rate ..20.0 20.0 20.0 20.0 20.0 20.0 20.0 20.0 Enable Disconnection ....Initiate Wide Negotiation .... Option Listed Below Have NO EFFECT if Multiple BIOS Support is Disabled Send Start Unit Command ..

  • Page 142: Maximum Synchronous Transfer Rate

    Additional Options Maximum Synchronous Transfer Rate The maximum synchronous transfer rate that the adapter will negotiate is defined by this setting. The default rates of the transfer are defined in the above SCSI Device Configuration menu. The adapter automatically negotiates for the rate requested by the device.

  • Page 143: Advanced Configuration Options

    VMIVME-7697 Product Manual Advanced Configuration Options The SCSI BIOS includes advanced configuration setting. Users are discouraged from changing these options. The default settings are included in the following menu. Advanced Configuration Options Option Listed Below Have NO EFFECT if Multiple BIOS Support is Disabled Host Adapter BIOS (Configuration Utility Reserves BIOS Space) ..

  • Page 144: Extended Bios Translation For Dos Drives > 1 Gbyte

    This option appears only if the BIOS is configured to include Ultra SCSI support. To support Ultra SCSI speeds, the option must be Enabled, and the Jumper J14 on the VMIVME-7697 CPU board must be open. The default entry is Disabled and the Jumper J14 is installed.

  • Page 145: Scsi Disk Utilities

    VMIVME-7697 Product Manual SCSI Disk Utilities The SCSI Disk Utilities allow the users to perform disk setup and configuration operations. These operations include listing SCSI IDs of the devices on the host adapter, formatting SCSI disk drives, and checking drives for defects.

  • Page 146: Formatting A Disk

    SCSI Disk Utilities Formatting a Disk Most SCSI drives are preformatted; however, if formatting is necessary, the operator can use the SCSI BIOS to perform a low-level format on the drive. The formatting is compatible with most SCSI disk drives. The operating system’s partitioning and high-level formatting utilities, such as MS-DOS fdisk and format, require that a disk have a low-level format.
  • Page 147 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 148 This appendix provides the user with the information needed to develop custom applications for the VMIVME-7697. The CPU board on the VMIVME-7697 is unique in that the BIOS can not be removed; it must be used in the initial boot cycle. A custom application, like a revised operating system for example, can only begin to operate after the BIOS has finished initializing the CPU.

  • Page 149: Bios Operations

    BIOS and reconfigure the system or it could accept what the BIOS initialized. BIOS Control Overview There are two areas on the VMIVME-7697 in which the user must be familiar in order to override the initial BIOS configuration. These include the device addresses and the device interrupts.

  • Page 150: Figure F-1 Vmivme-7697 Block Diagram

    128 Kbyte PCI-to-EIDE with NVRAM Parallel Port Flash BIOS Watchdog Timer Hard NVRAM Controller DS1384 Floppy Drive Drive FDC37C67X PS/2 Keyboard PS/2 Mouse Figure F-1 VMIVME-7697 Block Diagram Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 151: Data Book References

    2. Intel 21143 10/100 Mb/s Ethernet LAN Controller Intel www.intel.com 3. VMIVME-7697 User Manual 500-007697-000 Product Manual 500-007697-001 VMIVME-7697, Tundra Universe II-Based VMEbus Interface Option Product Manual 4. PCI Local Bus Specification, Rev. 2.1 PCI Special Interest Group P.O. Box 14070 Portland, OR 97214 (800) 433-5177 (U.S.) (503) 797-4207 (International) (503) 234-6762 (FAX)
  • Page 152 BIOS Operations 10. Intel 440Bx AGP Set: 82443 Bx Host Bridge Controller April 1998, Order Number 290633-001 Intel Corp. P.O. Box 58119 Santa Clara CA 95052-8119 (408) 765-8080 www.intel.com 11. Adaptec A-IC-7880 Ultra/FAST SCSI Host Adapter Adaptec Inc. 691 South Milpitas Blvd. Milpitas CA 95035 12.

  • Page 153: Table F-1 Isa Device Mapping Configuration

    64 Kbyte. ISA Devices The ISA devices on the VMIVME-7697 are configured by the BIOS at boot-up and fall under the realm of the standard PC/AT architecture. They are mapped in I/O address space within standard addresses and their interrupts are mapped to standard interrupt control registers.

  • Page 154: Table F-2 Pci Device Mapping Configuration

    PCI devices are fully configured under I/O and/or Memory address space. Table F-3 describes the PCI bus devices that are on-board the VMIVME-7697 along with each device’s configuration spectrum. The PCI bus includes three physical address spaces. As with ISA bus, PCI bus supports Memory and I/O address space, but PCI bus includes an additional Configuration address space.

  • Page 155: Device Interrupt Definition

    ISA Device Interrupt Map The VMIVME-7697 BIOS maps the IRQx lines to the appropriate device per the standard ISA architecture. Reference Figure F-2 on page 155. This initialization operation cannot be changed; however, a custom application could reroute the interrupt configuration after the BIOS has completed the initial configuration cycle.

  • Page 156: Figure F-2 Bios Default Connections For The Pc Interrupt Logic Controller

    Device Interrupt Definition INTR 8259 MASTER-PORTS $020-$021 Interrupt Com 2 Floppy Timer Keybd Com 1 Timer Lpt 1 8-15 Control IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 8259 SLAVE- PORTS $0A0-$0A1 Real-Tm IRQ2 Mouse Math Flash Hard Drv Drive Clock Coproc IRQ8...

  • Page 157: Table F-3 Device Pci Interrupt Mapping By The Bios

    VMIVME-7697 Product Manual PCI Device Interrupt Map The PCI bus-based external devices include the PCI expansion site, the PCI-to-VMEbus bridge, and the VGA reserved connection. The default BIOS maps these external devices to the PCI Interrupt Request (PIRQx) lines of the PIIX4. This...

  • Page 158: Table F-4 Default Pirqx To Irqx Bios Mapping

    Device Interrupt Definition The motherboard accepts these PCI device interrupts through the PCI interrupt mapper function. The BIOS default maps the PCI Interrupt Request (PIRQx) external device lines to one of the available slave PIC Interrupt Request lines, IRQ (9, 10, 11, 12, or 15).
  • Page 159 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 160 Introduction This appendix provides listings of a library of sample code that the programmer may utilize to build applications. These files are provided to the VMIVME-7697 user on disk 320-500043-007, Sample Application C Code for the VMIVME-7697, included in the distribution disk set.

  • Page 161: Directory Sram

    VMIVME-7697 Product Manual Directory SRAM The file in this directory can be used to test the integrity of the battery backed SRAM. The additional files in this directory (Flat.c, Flat.h, Pci.c, and Pci.h) should be linked to Sram.c for compiling.
  • Page 162 Directory SRAM exit( 1 ); /* get SRAM base address from config area */ test_int = read_configuration_area(READ_CONFIG_DWORD, bus, dev_func, 0x1C, &temp_dword); if(test_int != SUCCESSFUL) printf(“\nUnable to read SRAM BASE ADDRESS @ 0x1C in config space\n”); exit( 1 ); sram_base = temp_dword & 0xFFFFFFF0; extend_seg();...

  • Page 163: Directory Timers

    This directory contains sample code useful in the creation of applications involving the VMIVME-7697’s three software controlled 16-bit timers. The code is written for the control of a single timer, but can be utilized in generating code for any timer configuration.
  • Page 164 Directory Timers unsigned char tmr_status; unsigned char int_line; FPTR timers_base; void main( void ) int i; int test_int; unsigned long temp_dword; unsigned char bus, dev_func; /* try to locate the 7697 device on the PCI bus */ test_int = find_pci_device(DID_7697, VID_7697, 0, &bus, &dev_func);...
  • Page 165 VMIVME-7697 Product Manual int_line = 0x05; extend_seg(); a20( 1 ); /* setup timers interrupt service routine */ init_timer_int(); /* set cascaded counters to independent */ fw_byte( timers_base + EXT_TMR_CNTL, ( TCS_B0_16 | TCS_B1_16 | TCS_B2_16 ) ); /* use the load_counter function to setup the counters */ /* load all three banks counter 1 with max (65.54 ms) */...
  • Page 166 Directory Timers fw_byte( timers_base + EXT_TMR_CNTL, ( TCS_B0_32 | TCS_B1_32 | TCS_B2_32 ) ); /* load all three banks counters 1 & 2 with max and one (132 ms) */ /* counter 0 must be set to 0 */ load_counter( 0, 0, 0x0000 ); load_counter( 0, 1, 0xFFFF );...

  • Page 167: File: Timers.c

    VMIVME-7697 Product Manual ** FILE: TIMERS.C ** FILE: TIMERS.C #include <stdlib.h> #include <stdio.h> #include <dos.h> #include <ctype.h> #include <conio.h> #include “timers.h” #include “flat.h” #define IRQ5 0x0D #define IRQ9 0x71 #define IRQA 0x72 #define IRQB 0x73 #define IRQC 0x74 #define IRQD...
  • Page 168 Directory Timers /* global variables */ extern unsigned char int_line; extern unsigned char tmr_status; extern FPTR timers_base; unsigned char pic2_org; unsigned char pic1_org; void far interrupt (* old_vect)(void); /*******************************************************************/ /* init_timer_int() /* purpose: Using the interrupt assigned, the original vector is */ saved and the vector to the new ISR is installed.
  • Page 169 VMIVME-7697 Product Manual if( int_line == 0x5 ) old_vect = getvect( IRQ5 ); /* save vector for IRQ 5 */ setvect( IRQ5, irq_rcvd ); /* enable interrupt 5 */ outp(0x21, (pic1_org & 0xDF) ); else if( int_line == 0x9 ) old_vect = getvect( IRQ9 );...
  • Page 170 Directory Timers /* enable interrupt 11 */ outp(0xa1, (pic2_org & 0xF7) ); else if( int_line == 0xC ) old_vect = getvect( IRQC ); /* save vector for IRQ 12 */ setvect( IRQC, irq_rcvd ); /* enable interrupt 12 */ outp(0xa1, (pic2_org & 0xEF) ); else if( int_line == 0xD ) old_vect = getvect( IRQD );...
  • Page 171 VMIVME-7697 Product Manual old_vect = getvect( IRQF ); /* save vector for IRQ 15 */ setvect( IRQC, irq_rcvd ); /* enable interrupt 15 */ outp(0xa1, (pic2_org & 0x7F) ); enable(); } /* init_timer_int */ /*******************************************************************/ /* restore_orig_int() /* purpose: Using the interrupt assigned, the original vector is */ restored and the programmable-interrupt-controller */ is disabled.
  • Page 172 Directory Timers outp(0x21, pic1_org); if( int_line == 0x5 ) setvect( IRQ5, old_vect ); else if( int_line == 0x9 ) setvect( IRQ9, old_vect ); else if( int_line == 0xA ) setvect( IRQA, old_vect ); else if( int_line == 0xB ) setvect( IRQB, old_vect ); else if( int_line == 0xC ) setvect( IRQC, old_vect );...
  • Page 173 VMIVME-7697 Product Manual else if( int_line == 0xE ) setvect( IRQE, old_vect ); else if( int_line == 0xF ) setvect( IRQF, old_vect ); enable(); } /* restore_orig_int */ /*******************************************************************/ /* load_counter() /* purpose: Loads the appropriate counter in the appropriate bank with the count passed in.
  • Page 174 Directory Timers lsb = count & 0xff; msb = count >> 8; switch( bank ) case 0: /* select BANK 0 */ switch( counter ) case 0: /* select counter 0, LSB then MSB, mode 3 */ fw_byte( timers_base + BANK0_CNTL, (CW_SC0 | CW_LSBMSB | CW_M3) ); fw_byte( timers_base + BANK0_CNTR0, (unsigned char) lsb );...
  • Page 175 VMIVME-7697 Product Manual fw_byte( timers_base + BANK1_CNTL, (CW_SC0 | CW_LSBMSB | CW_M3) ); fw_byte( timers_base + BANK1_CNTR0, (unsigned char) lsb ); fw_byte( timers_base + BANK1_CNTR0, (unsigned char) msb ); break; case 1: /* select counter 1, LSB then MSB, mode 5 */ fw_byte( timers_base + BANK1_CNTL, (CW_SC1 | CW_LSBMSB | CW_M5) );...
  • Page 176 Directory Timers break; case 2: /* select counter 2, LSB then MSB, mode 5 */ fw_byte( timers_base + BANK2_CNTL, (CW_SC2 | CW_LSBMSB | CW_M5) ); fw_byte( timers_base + BANK2_CNTR2, (unsigned char) lsb ); fw_byte( timers_base + BANK2_CNTR2, (unsigned char) msb ); break;...
  • Page 177 VMIVME-7697 Product Manual switch( bank ) case 0: /* select BANK 0 */ switch( counter ) case 0: /* select counter 0, LSB then MSB */ fw_byte( timers_base + BANK0_CNTL, ( CW_RBC | CW_RB_CNT | CW_RB_STAT | CW_RB_C0 ) );...
  • Page 178 Directory Timers *count = ( lsb | msb ); break; break; case 1: /* select BANK 1 */ switch( counter ) case 0: /* select counter 0, LSB then MSB */ fw_byte( timers_base + BANK1_CNTL, ( CW_RBC | CW_RB_CNT | CW_RB_STAT | CW_RB_C0 ) );...
  • Page 179 VMIVME-7697 Product Manual msb = fr_byte( timers_base + BANK1_CNTR2 ) & 0xFF; msb = msb << 8; *count = ( lsb | msb ); break; break; case 2: /* select BANK 2 */ switch( counter ) case 0: /* select counter 0, LSB then MSB */ fw_byte( timers_base + BANK2_CNTL, ( CW_RBC | CW_RB_CNT | CW_RB_STAT | CW_RB_C0 ) );...
  • Page 180 Directory Timers *status = fr_byte( timers_base + BANK2_CNTR2 ) & 0xFF; lsb = fr_byte( timers_base + BANK2_CNTR2 ) & 0xFF; msb = fr_byte( timers_base + BANK2_CNTR2 ) & 0xFF; msb = msb << 8; *count = ( lsb | msb ); break;...
  • Page 181 VMIVME-7697 Product Manual push ebx /* read status */ tmr_status = fr_byte( timers_base + EXT_TMR_TIS ) & 0xFF; /* Non specific end of interrupt to PIC */ outp(0x20, 0x20); /* Master end of irq command */ asm { .386P pop ebx pop eax enable();...

  • Page 182: Timers.h

    Directory Timers TIMERS.H /*****************************************************************************/ /* FILE: TIMERS.H Header file for the 7697 timers /*****************************************************************************/ #define BANK0_CNTR0 0x00 /* Timer bank 0 counter 0 #define BANK0_CNTR1 0x04 /* Timer bank 0 counter 1 #define BANK0_CNTR2 0x08 /* Timer bank 0 counter 2 #define BANK0_CNTL 0x0C /* Timer bank 0 control...
  • Page 183 VMIVME-7697 Product Manual #define TCS_B1_32 0x02 /* RW 1 = 32 bit cascade 0 = 16 bit */ #define TCS_B0_32 0x01 /* RW 1 = 32 bit cascade 0 = 16 bit */ #define TCS_B0_16 0x00 /* RW 1 = 32 bit cascade 0 = 16 bit */...
  • Page 184 Directory Timers #define CW_LSB 0x10 /* W LSB only #define CW_MSB 0x20 /* W MSB only #define CW_LSBMSB 0x30 /* W LSB first then MSB #define CW_M0 0x00 /* W Mode 0 #define CW_M1 0x02 /* W Mode 1 #define CW_M2 0x04 /* W Mode 2 #define...

  • Page 185: Directory Vme

    VMIVME-7697 Product Manual Directory VME This directory contains the files used to setup the universe chip with one PCI-TO-VME window and enable Universe II registers to be accessed from the VME to allow mailbox access. ** FILE: CPU.C /****************************************************************************/ /* FILE: CPU.C /* Setup the universe chip with one PCI-TO-VME window and enable universe */ /* registers to be accessed from VME to allow mailbox access.
  • Page 186 Directory VME #define IRQC 0x74 /* Int. No. for hardware int C */ #define IRQD 0x75 /* Int. No. for hardware int D */ #define IRQE 0x76 /* Int. No. for hardware int E */ #define IRQF 0x77 /* Int. No. for hardware int F */ /* function prototypes */ void far interrupt irq_rcvd( void );...
  • Page 187 VMIVME-7697 Product Manual /* try to locate the UNIVERSE device on the PCI bus */ test_int = find_pci_device(UNIVERSE_DID, UNIVERSE_VID, 0, &bus, &dev_func); if(test_int == SUCCESSFUL) test_int = read_configuration_area( READ_CONFIG_DWORD, bus, dev_func, 0x10, &temp_dword ); if(test_int == SUCCESSFUL) un_regs = (FPTR) temp_dword;...
  • Page 188 Directory VME exit( 1 ); /* setup protected mode */ extend_seg(); a20( 1 ); mb0_msg = 0; mb1_msg = 0; mb2_msg = 0; mb3_msg = 0; init_int(); /* 32K PCI slave window at 0x10000000 to VME A16 0x0000 user data */ fw_long( un_regs + LSI0_BS_A, PCI_BASE16 );...
  • Page 189 VMIVME-7697 Product Manual /* place additional code here */ do_exit( 0 ); } /* end main */ void do_exit( int xcode ) /* disable all windows and interrupts */ fw_long( un_regs + LSI0_CTL_A, 0 ); fw_long( un_regs + LSI1_CTL_A, 0 );...
  • Page 190 Directory VME a20( 0 ); exit( xcode ); } /* end do_exit */ /*******************************************************************/ /* init_int() /* purpose: Using the interrupt assigned, the original vector is */ saved and the vector to the new ISR is installed. The */ programmable-interrupt-controller (PIC) is enabled. */ /*******************************************************************/ /* parameters: none /*******************************************************************/...
  • Page 191 VMIVME-7697 Product Manual break; case 0xa: old_vect = getvect( IRQA ); /* save vector for IRQ 10 */ setvect( IRQA, irq_rcvd ); /* enable interrupt 10 */ outp(0xa1, (pic2_org & 0xFB) ); break; case 0xb: old_vect = getvect( IRQB ); /* save vector for IRQ 11 */ setvect( IRQB, irq_rcvd );...
  • Page 192 Directory VME setvect( IRQE, irq_rcvd ); /* enable interrupt 14 */ outp(0xa1, (pic2_org & 0xBF) ); break; case 0xf: old_vect = getvect( IRQF ); /* save vector for IRQ 15 */ setvect( IRQF, irq_rcvd ); /* enable interrupt 15 */ outp(0xa1, (pic2_org &...
  • Page 193 VMIVME-7697 Product Manual is restored to its original settings. /* Prerequisite: The interrupt line to be used must have already been loaded in the global variable. /*******************************************************************/ /* parameters: none /*******************************************************************/ /* return value: none /*******************************************************************/ void restore_orig_int( void ) disable();...
  • Page 194 Directory VME break; case 0xd: setvect( IRQD, old_vect ); break; case 0xe: setvect( IRQE, old_vect ); break; case 0xf: setvect( IRQF, old_vect ); break; } /* end switch */ fw_long( un_regs + LINT_EN_A, 0 ); /* disable all interrupts */ enable();...
  • Page 195 VMIVME-7697 Product Manual void interrupt irq_rcvd( void ) unsigned long lint_enable, tmp_status; disable(); asm { .386P push eax push ebx int_status = fr_long( un_regs + LINT_STAT_A ); /* read interrupt status */ fw_long( un_regs + LINT_STAT_A, int_status ); /* clear status */ /* check for mailbox interrupt */ if( int_status &...
  • Page 196 Directory VME if( int_status & LINT_STAT_MBOX3 ) mb3_msg = fr_long( un_regs + MBOX3_A ); /* disable MB ints */ lint_enable = fr_long( un_regs + LINT_EN_A ); lint_enable &= ~(LINT_EN_MBOX3 | LINT_EN_MBOX2 | LINT_EN_MBOX1 | LINT_EN_MBOX0); fw_long( un_regs + LINT_EN_A, lint_enable ); /* clear all mailboxes */ fw_long( un_regs + MBOX0_A, 0 );...
  • Page 197 VMIVME-7697 Product Manual enable(); Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...

  • Page 198: File: Cpu.h

    Directory VME ** FILE: CPU.H typedef unsigned char Byte; typedef unsigned short Word; typedef unsigned long Long; /* universe Device ID and Vendor ID */ #define UNIVERSE_VID 0x10E3 #define UNIVERSE_DID 0x0000 /* CPU specific bits located at I/O 0x400 */ #define CPUREGS 0xD800E /* CPU regs located at mem 0xD800E */ #define MEC_BE...

  • Page 199: File: Universe.h

    VMIVME-7697 Product Manual ** FILE: UNIVERSE.H ** file: universe.h ** header file for the universe II chip register definitions typedef volatile struct universe_regs { unsigned long pci_id; /* PCI device ID vendor ID unsigned long pci_csr; /* PCI config control/status reg unsigned long pci_class;...
  • Page 200 Directory VME unsigned long ur1; /* reserved unsigned long lsi2_ctl; /* PCI slave image 2 control reg unsigned long lsi2_bs; /* PCI slave image 2 base address reg unsigned long lsi2_bd; /* PCI slave image 2 bound address reg unsigned long lsi2_to; /* PCI slave image 2 translation offset reg */ unsigned long ur2;...
  • Page 201 VMIVME-7697 Product Manual unsigned long lsi6_bs; /* PCI slave image 6 base address reg unsigned long lsi6_bd; /* PCI slave image 6 bound address reg unsigned long lsi6_to; /* PCI slave image 6 translation offset reg */ unsigned long ur7;...
  • Page 202 Directory VME unsigned long v4_statid; /* VME interrupt status/ID in IRQ4 unsigned long v5_statid; /* VME interrupt status/ID in IRQ5 unsigned long v6_statid; /* VME interrupt status/ID in IRQ6 unsigned long v7_statid; /* VME interrupt status/ID in IRQ7 unsigned long lint_map2; /* PCI interrupt map2 unsigned long vint_map2;...
  • Page 203 VMIVME-7697 Product Manual unsigned long urH; /* reserved unsigned long vsi3_ctl; /* VMEbus slave image 3 control reg unsigned long vsi3_bs; /* VMEbus slave image 3 base address reg unsigned long vsi3_bd; /* VMEbus slave image 3 bound address reg unsigned long vsi3_to;...
  • Page 204 Directory VME unsigned long vsi7_bs; /* VMEbus slave image 7 base address reg unsigned long vsi7_bd; /* VMEbus slave image 7 bound address reg unsigned long vsi7_to; /* VMEbus slave image 7 translation offset */ unsigned long urP[0x05]; /* reserved unsigned long v_cr_csr;...
  • Page 205 VMIVME-7697 Product Manual #define LSI3_TO_A 0x148 /* PCI slave image 3 translation offset reg */ #define SCYC_CTL_A 0x170 /* PCI special cycle control reg #define SCYC_ADDR_A 0x174 /* PCI special cycle PCI address reg #define SCYC_EN_A 0x178 /* PCI special cycle swap/compare enable reg */...
  • Page 206 Directory VME #define D_LLUE_A 0x224 /* DMA linked list update enable reg #define LINT_EN_A 0x300 /* PCI interrupt enable #define LINT_STAT_A 0x304 /* PCI interrupt status #define LINT_MAP0_A 0x308 /* PCI interrupt map0 #define LINT_MAP1_A 0x30C /* PCI interrupt map1 #define VINT_EN_A 0x310 /* VME interrupt enable #define VINT_STAT_A 0x314 /* VME interrupt status #define VINT_MAP0_A 0x318 /* VME interrupt map0...
  • Page 207 VMIVME-7697 Product Manual #define VSI0_TO_A 0xF0C /* VMEbus slave image 0 translation offset */ #define VSI1_CTL_A 0xF14 /* VMEbus slave image 1 control reg #define VSI1_BS_A 0xF18 /* VMEbus slave image 1 base address reg #define VSI1_BD_A 0xF1C /* VMEbus slave image 1 bound address reg...
  • Page 208 Directory VME #define VSI6_TO_A 0xFC4 /* VMEbus slave image 6 translation offset */ #define VSI7_CTL_A 0xFCC /* VMEbus slave image 7 control reg #define VSI7_BS_A 0xFD0 /* VMEbus slave image 7 base address reg #define VSI7_BD_A 0xFD4 /* VMEbus slave image 7 bound address reg #define VSI7_TO_A 0xFD8 /* VMEbus slave image 7 translation offset */ #define V_CR_CSR_A 0xFF0 /* VMEbus CR/CSR reserved #define VCSR_CLR_A 0xFF4 /* VMEbus CSR bit clear reg...
  • Page 209 VMIVME-7697 Product Manual /* pci_csr - PCI configuration space control and status register */ #define PCI_CSR_D_PE 0x80000000 /* R/WC detected parity error #define PCI_CSR_S_SERR 0x40000000 /* R/WC signalled SERR* #define PCI_CSR_R_MA 0x20000000 /* R/WC received master abort #define PCI_CSR_R_TA 0x10000000 /* R/WC received target abort...
  • Page 210 Directory VME #define PCI_MISC0_LAYOUT 0x007F0000 /* R configuration space layout MASK #define PCI_MISC0_LTIMER 0x0000F800 /* R/W latency timer MASK /* pci_bs - PCI configuration base address register */ #define PCI_BS_BS 0xFFFF0000 /* R PCI base address MASK #define PCI_BS_SPACE_M 0x00000000 /* R PCI address space memory #define PCI_BS_SPACE_IO 0x00000001 /* R PCI address space I/O /* pci_misc1 - PCI configuration miscellaneous 1 register */...
  • Page 211 VMIVME-7697 Product Manual #define LSI_CTL_VAS_U2 0x00070000 /* R/W VMEbus address space USER2 #define LSI_CTL_PGM_D 0x00000000 /* R/W VMEbus data AM code #define LSI_CTL_PGM_P 0x00004000 /* R/W VMEbus program AM code #define LSI_CTL_SUPER 0x00001000 /* R/W VMEbus supervisory AM code #define...
  • Page 212 Directory VME #define LSI0_TO 0xFFFFF000 /* R/W PCI slave image 0 xfer offset MASK */ #define LSI1_TO 0xFFFF0000 /* R/W PCI slave image 1 xfer offset MASK */ #define LSI2_TO 0xFFFF0000 /* R/W PCI slave image 2 xfer offset MASK */ #define LSI3_TO 0xFFFF0000 /* R/W PCI slave image 3 xfer offset MASK */ #define...
  • Page 213 VMIVME-7697 Product Manual #define LMISC_CRT_1 0x10000000 /* R/W coupled request timer 128 us #define LMISC_CRT_2 0x20000000 /* R/W coupled request timer 256 us #define LMISC_CRT_3 0x30000000 /* R/W coupled request timer 512 us #define LMISC_CRT_4 0x40000000 /* R/W coupled request timer 1024 us...
  • Page 214 Directory VME /* laerr - R PCI address error log 0x00000000 */ #define LAERR 0xFFFFFFFF /* PCI address error log MASK /* dctl - DMA transfer control register */ #define DCTL_L2V_I 0x00000000 /* R/W direction: VME -> PCI #define DCTL_L2V_O 0x80000000 /* R/W direction: PCI -> VME #define DCTL_VDW_08 0x00000000 /* R/W VMEbus max data width D08 #define...
  • Page 215 VMIVME-7697 Product Manual /* dva - DMA VMEbus address register 0x0000000X */ #define 0xFFFFFFFF /* R/W DMA VMEbus address MASK /* dcpp - DMA command packet pointer 0x0000000X */ #define DCPP 0xFFFFFFF8 /* R/W DMA command packet pointer MASK */...
  • Page 216 Directory VME #define DGCS_STOP 0x00004000 /* R/WC DMA stopped flag #define DGCS_HALT 0x00002000 /* R/WC DMA halted flag #define DGCS_DONE 0x00000800 /* R/WC DMA transfers complete flag */ #define DGCS_LERR 0x00000400 /* R/WC DMA PCi bus error #define DGCS_VERR 0x00000200 /* R/WC DMA VMEbus error #define DGCS_P_ERR 0x00000100 /* R/WC protocol error...
  • Page 217 VMIVME-7697 Product Manual #define LINT_EN_DMA 0x00000100 /* R/W PCI DMA interrupt enable #define LINT_EN_VIRQ7 0x00000080 /* R/W VIRQ7 interrupt enable #define LINT_EN_VIRQ6 0x00000040 /* R/W VIRQ6 interrupt enable #define LINT_EN_VIRQ5 0x00000030 /* R/W VIRQ5 interrupt enable #define LINT_EN_VIRQ4 0x00000010 /* R/W VIRQ4 interrupt enable...
  • Page 218 Directory VME #define LINT_STAT_VIRQ2 0x00000004 /* R/WC VIRQ2 interrupt received #define LINT_STAT_VIRQ1 0x00000002 /* R/WC VIRQ1 interrupt received #define LINT_STAT_VOWN 0x00000001 /* R/WC VOWN interrupt received /* lint_map0 - PCI interrupt map 0 register */ #define LINT_MAP0_VIRQ7_0 0x00000000 /* R/W PCI int LINT#0 for VME IRQ7 #define LINT_MAP0_VIRQ7_1 0x10000000 /* R/W PCI int LINT#1 for VME IRQ7 #define...
  • Page 219 VMIVME-7697 Product Manual #define LINT_MAP0_VIRQ5_0 0x00000000 /* R/W PCI int LINT#0 for VME IRQ5 #define LINT_MAP0_VIRQ5_1 0x00100000 /* R/W PCI int LINT#1 for VME IRQ5 #define LINT_MAP0_VIRQ5_2 0x00200000 /* R/W PCI int LINT#2 for VME IRQ5 #define LINT_MAP0_VIRQ5_3 0x00300000 /* R/W PCI int LINT#3 for VME IRQ5...
  • Page 220 Directory VME #define LINT_MAP0_VIRQ3_3 0x00003000 /* R/W PCI int LINT#3 for VME IRQ3 #define LINT_MAP0_VIRQ3_4 0x00004000 /* R/W PCI int LINT#4 for VME IRQ3 #define LINT_MAP0_VIRQ3_5 0x00005000 /* R/W PCI int LINT#5 for VME IRQ3 #define LINT_MAP0_VIRQ3_6 0x00006000 /* R/W PCI int LINT#6 for VME IRQ3 #define LINT_MAP0_VIRQ3_7 0x00007000 /* R/W PCI int LINT#7 for VME IRQ3 #define...
  • Page 221 VMIVME-7697 Product Manual #define LINT_MAP0_VIRQ1_6 0x00000060 /* R/W PCI int LINT#6 for VME IRQ1 #define LINT_MAP0_VIRQ1_7 0x00000070 /* R/W PCI int LINT#7 for VME IRQ1 #define LINT_MAP0_VOWN_0 0x00000000 /* R/W PCI int LINT#0 for VME OWN */ #define LINT_MAP0_VOWN_1 0x00000001 /* R/W PCI int LINT#1 for VME...
  • Page 222 Directory VME #define LINT_MAP1_SYSFAIL_0 0x00000000 /* R/W PCI int LINT#0 for SYSFAIL #define LINT_MAP1_SYSFAIL_1 0x01000000 /* R/W PCI int LINT#1 for SYSFAIL #define LINT_MAP1_SYSFAIL_2 0x02000000 /* R/W PCI int LINT#2 for SYSFAIL #define LINT_MAP1_SYSFAIL_3 0x03000000 /* R/W PCI int LINT#3 for SYSFAIL #define LINT_MAP1_SYSFAIL_4 0x04000000 /* R/W PCI int LINT#4 for SYSFAIL #define...
  • Page 223 VMIVME-7697 Product Manual #define LINT_MAP1_SW_IACK_3 0x00030000 /* R/W PCI int LINT#3 for SW_IACK */ #define LINT_MAP1_SW_IACK_4 0x00040000 /* R/W PCI int LINT#4 for SW_IACK */ #define LINT_MAP1_SW_IACK_5 0x00050000 /* R/W PCI int LINT#5 for SW_IACK */ #define LINT_MAP1_SW_IACK_6 0x00060000 /* R/W PCI int LINT#6 for...
  • Page 224 Directory VME /* vint_en - VMEbus interrupt enable register */ #define VINT_EN_SW7 0x80000000 /* R/W enable VMEbus int SW7 #define VINT_EN_SW6 0x40000000 /* R/W enable VMEbus int SW6 #define VINT_EN_SW5 0x20000000 /* R/W enable VMEbus int SW5 #define VINT_EN_SW4 0x10000000 /* R/W enable VMEbus int SW4 #define VINT_EN_SW3 0x08000000 /* R/W enable VMEbus int SW3...
  • Page 225 VMIVME-7697 Product Manual #define VINT_STAT_SW5 0x20000000 /* R/W VMEbus int SW5 #define VINT_STAT_SW4 0x10000000 /* R/W VMEbus int SW4 #define VINT_STAT_SW3 0x08000000 /* R/W VMEbus int SW3 #define VINT_STAT_SW2 0x04000000 /* R/W VMEbus int SW2 #define VINT_STAT_SW1 0x02000000 /* R/W VMEbus int SW1...
  • Page 226 Directory VME #define VINT_MAP0_LINT6_D 0x00000000 /* R/W VME int disable for LINT6 #define VINT_MAP0_LINT6_1 0x01000000 /* R/W VME int 1 for LINT6 #define VINT_MAP0_LINT6_2 0x02000000 /* R/W VME int 2 for LINT6 #define VINT_MAP0_LINT6_3 0x03000000 /* R/W VME int 3 for LINT6 #define VINT_MAP0_LINT6_4 0x04000000 /* R/W VME int 4 for LINT6 #define...
  • Page 227 VMIVME-7697 Product Manual #define VINT_MAP0_LINT3_5 0x00005000 /* R/W VME int 5 for LINT3 #define VINT_MAP0_LINT3_6 0x00006000 /* R/W VME int 6 for LINT3 #define VINT_MAP0_LINT3_7 0x00007000 /* R/W VME int 7 for LINT3 #define VINT_MAP0_LINT2_D 0x00000000 /* R/W VME int disable for LINT2...
  • Page 228 Directory VME #define VINT_MAP1_SW_IACK_D 0x00000000 /* R/W VME int disable for SW_IACK */ #define VINT_MAP1_SW_IACK_1 0x00010000 /* R/W VME int 1 for SW_IACK #define VINT_MAP1_SW_IACK_2 0x00020000 /* R/W VME int 2 for SW_IACK #define VINT_MAP1_SW_IACK_3 0x00030000 /* R/W VME int 3 for SW_IACK #define VINT_MAP1_SW_IACK_4 0x00040000 /* R/W VME int 4 for SW_IACK #define...
  • Page 229 VMIVME-7697 Product Manual #define VINT_MAP1_DMA_1 0x00000001 /* R/W VME int 1 for DMA #define VINT_MAP1_DMA_2 0x00000002 /* R/W VME int 2 for DMA #define VINT_MAP1_DMA_3 0x00000003 /* R/W VME int 3 for DMA #define VINT_MAP1_DMA_4 0x00000004 /* R/W VME int 4 for DMA...
  • Page 230 Directory VME #define LINT_MAP2_LM3_6 0x60000000 /* R/W PCI int LINT#6 for LOC MON3 #define LINT_MAP2_LM3_7 0x70000000 /* R/W PCI int LINT#7 for LOC MON3 #define LINT_MAP2_LM2_0 0x00000000 /* R/W PCI int LINT#0 for LOC MON2 #define LINT_MAP2_LM2_1 0x01000000 /* R/W PCI int LINT#1 for LOC MON2 #define LINT_MAP2_LM2_2 0x02000000 /* R/W PCI int LINT#2 for LOC MON2...
  • Page 231 VMIVME-7697 Product Manual #define LINT_MAP2_LM0_1 0x00010000 /* R/W PCI int LINT#1 for LOC_MON0 */ #define LINT_MAP2_LM0_2 0x00020000 /* R/W PCI int LINT#2 for LOC_MON0 */ #define LINT_MAP2_LM0_3 0x00030000 /* R/W PCI int LINT#3 for LOC_MON0 */ #define LINT_MAP2_LM0_4 0x00040000 /* R/W PCI int LINT#4 for...
  • Page 232 Directory VME #define LINT_MAP2_MB2_4 0x00000400 /* R/W PCI int LINT#4 for MAILBOX2 #define LINT_MAP2_MB2_5 0x00000500 /* R/W PCI int LINT#5 for MAILBOX2 #define LINT_MAP2_MB2_6 0x00000600 /* R/W PCI int LINT#6 for MAILBOX2 #define LINT_MAP2_MB2_7 0x00000700 /* R/W PCI int LINT#7 for MAILBOX2 #define LINT_MAP2_MB1_0 0x00000000 /* R/W PCI int LINT#0 for MAILBOX1...
  • Page 233 VMIVME-7697 Product Manual #define LINT_MAP2_MB0_7 0x00000007 /* R/W PCI int LINT#7 for MAILBOX0 /* vint_map2 - vme interrupt Map 2 register */ #define VINT_MAP2_MB3_1 0x00001000 /* R/W VME int VIRQ#1 for MAILBOX3 */ #define VINT_MAP2_MB3_2 0x00002000 /* R/W VME int VIRQ#2 for...
  • Page 234 Directory VME #define VINT_MAP2_MB1_4 0x00000040 /* R/W VME int VIRQ#4 for MAILBOX1 */ #define VINT_MAP2_MB1_5 0x00000050 /* R/W VME int VIRQ#5 for MAILBOX1 */ #define VINT_MAP2_MB1_6 0x00000060 /* R/W VME int VIRQ#6 for MAILBOX1 */ #define VINT_MAP2_MB1_7 0x00000070 /* R/W VME int VIRQ#7 for MAILBOX1 */ #define VINT_MAP2_MB0_1...
  • Page 235 VMIVME-7697 Product Manual #define MAST_CTL_MRTRY_M 0xF0000000 /* Max PCI retries #define MAST_CTL_PWON_0 0x00000000 /* R/W posted write xfer count 128 */ #define MAST_CTL_PWON_1 0x01000000 /* R/W posted write xfer count 256 */ #define MAST_CTL_PWON_2 0x02000000 /* R/W posted write xfer count 512 */...
  • Page 236 Directory VME #define MISC_CTL_VBTO_1 0x10000000 /* R/W VME bus time out 16 us #define MISC_CTL_VBTO_2 0x20000000 /* R/W VME bus time out 32 us #define MISC_CTL_VBTO_3 0x30000000 /* R/W VME bus time out 64 us #define MISC_CTL_VBTO_4 0x40000000 /* R/W VME bus time out 128 us #define MISC_CTL_VBTO_5 0x50000000 /* R/W VME bus time out 256 us #define...
  • Page 237 VMIVME-7697 Product Manual /* user_am - user AM codes register */ #define USER_AM_1 0xFC000000 /* R/W user1 AM code MASK #define USER_AM_2 0x00FC0000 /* R/W user2 AM code MASK /* vsi[x]_ctl - VMEbus slave image 0 control register */ #define...
  • Page 238 Directory VME #define VSI2_BS 0xFFFF0000 /* R/W VME slave image 2 base add MASK */ #define VSI3_BS 0xFFFF0000 /* R/W VME slave image 3 base add MASK */ /* vsi[x]_bd - VMEbus slave image 0 bound address register */ #define VSI0_BD 0xFFFFF000 /* R/W VME slave image 0 bound add MASK */ #define...
  • Page 239 VMIVME-7697 Product Manual #define VRAI_CTL_AM_P 0x00800000 /* R/W AM code - program #define VRAI_CTL_AM_DP 0x00C00000 /* R/W AM code - both #define VRAI_CTL_AM_U 0x00100000 /* R/W AM code - non priv #define VRAI_CTL_AM_S 0x00200000 /* R/W AM code - supervisory...
  • Page 240 Directory VME #define VCSR_CLR_SYSFAIL 0x40000000 /* R/W VMEbus sysfail #define VCSR_CLR_FAIL 0x20000000 /* R board fail /* vcsr_set - VMEbus CSR bit set register */ #define VCSR_SET_RESET 0x80000000 /* R/W board reset #define VCSR_SET_SYSFAIL 0x40000000 /* R/W VMEbus sysfail #define VCSR_SET_FAIL 0x20000000 /* R board fail /* vcsr_bs - VMEbus CSR base address register */ #define...

  • Page 241: Directory Watchdog

    VMIVME-7697 Product Manual Directory WATCHDOG This directory contains sample code useful in the creation of applications involving the VMIVME-7697’s Watchdog Timer function as described in Chapter 4. ** FILE:WATCHDOG.H ** DS1384 REGISTER OFFSETS /* 7 6 5 4 3 2 1 0 */...

  • Page 242: File: Wd_Nmi.c

    Directory WATCHDOG ** FILE: WD_NMI.C #include <stdlib.h> #include <stdio.h> #include <dos.h> #include <time.h> #include <conio.h> #include <ctype.h> #include “watchdog.h” #include “flat.h” #include “pci.h” #define DID_7697 0x7697 /* Device ID #define VID_7697 0x114A /* Vendor ID /* TWRUN.C function prototypes */ void init_int( void );...
  • Page 243 VMIVME-7697 Product Manual test_int = find_pci_device(DID_7697, VID_7697, 0, &bus, &dev_func); if(test_int != SUCCESSFUL) printf(“\nUnable to locate 7697\n”); exit( 1 ); /* get watchdog base address from config area */ test_int = read_configuration_area(READ_CONFIG_DWORD, bus, dev_func, 0x24, &temp_dword); if(test_int != SUCCESSFUL) printf(“\nUnable to read WATCHDOG BASE ADDRESS @ 0x24 in config space\n”);...
  • Page 244 Directory WATCHDOG fw_byte( wd_base + 0x40, 0x01); /* enable watchdog in EPLD */ fw_byte( wd_base + WD_MSEC, 0x00 ); /* 00.00 seconds */ fw_byte( wd_base + WD_SEC, 0x05 ); /* 05.00 seconds */ fw_byte( wd_base + WD_CMD, WD_TE ); if( int_status ) break; delay( 1 );...
  • Page 245 VMIVME-7697 Product Manual fw_byte( wd_base + WD_MSEC, 0 ); /* load with 0 to disable */ fw_byte( wd_base + WD_SEC, 0 ); /* load with 0 to disable */ fw_byte( wd_base + WD_CMD, ( WD_TE | WD_WAM ) ); /* allow update with 0 time */ fw_byte( wd_base + WD_CMD, WD_WAM );...
  • Page 246 Directory WATCHDOG disable(); old_nmi_vect = getvect( 2 ); /* save vector for IRQ 09 */ setvect( 2, nmi_irq_rcvd ); /* arm nmi */ nmidat = inp( 0x61 ) & 0x0F; nmidat |= 0x04; outp( 0x61, nmidat ); /* set bit 2 to clear any previous condition */ nmidat &= 0x0B;...
  • Page 247 VMIVME-7697 Product Manual /*******************************************************************/ /* return value: none /*******************************************************************/ void restore_orig_int( void ) unsigned char nmidat; disable(); /* disable nmi */ outp( 0x70, 0x80 ); nmidat = inp( 0x61 ) & 0x0F; nmidat |= 0x04; outp( 0x61, nmidat ); /* set bit 2 to clear any previous condition */ setvect( 2, old_nmi_vect );...
  • Page 248 Directory WATCHDOG /* return value: none /*******************************************************************/ void interrupt nmi_irq_rcvd( void ) unsigned char nmidat; disable(); int_status = 1; /* set WatchDog Alarm Mask 1 - deactivated and update with 0 time */ fw_byte( wd_base + WD_CMD, ( WD_TE | WD_WAM ) ); fw_byte( wd_base + WD_MSEC, 0 );...

  • Page 249: File: Wd_Rst.c

    VMIVME-7697 Product Manual ** FILE: WD_RST.C #include <stdlib.h> #include <stdio.h> #include <dos.h> #include <time.h> #include <conio.h> #include <ctype.h> #include “watchdog.h” #include “flat.h” #include “pci.h” #define DID_7697 0x7697 /* Device ID #define VID_7697 0x114A /* Vendor ID void main( int argc, char * argv[] ) int test_int;...
  • Page 250 Directory WATCHDOG test_int = read_configuration_area(READ_CONFIG_DWORD, bus, dev_func, 0x24, &temp_dword); if(test_int != SUCCESSFUL) printf(“\nUnable to read WATCHDOG BASE ADDRESS @ 0x24 in config space\n”); exit( 1 ); wd_base = temp_dword & 0xFFFFFFF0; extend_seg(); a20( 1 ); /* set WatchDog Alarm Mask 1 - deactivated and update with 0 time */ fw_byte( wd_base + WD_CMD, ( WD_TE | WD_WAM ) );...
  • Page 251 VMIVME-7697 Product Manual /* set WatchDog Alarm Mask 1 - deactivated and update with 0 time */ fw_byte( wd_base + WD_CMD, ( WD_TE | WD_WAM ) ); fw_byte( wd_base + WD_MSEC, 0 ); /* load with 0 to disable */ fw_byte( wd_base + WD_SEC, 0 );...

  • Page 252: File: Wd_Run.c

    Directory WATCHDOG ** FILE: WD_RUN.C #include <stdlib.h> #include <stdio.h> #include <dos.h> #include <time.h> #include <conio.h> #include <ctype.h> #include “watchdog.h” #include “flat.h” #include “pci.h” #define DID_7697 0x7697 /* Device ID #define VID_7697 0x114A /* Vendor ID void main( int argc, char * argv[] ) int test_int, index;...
  • Page 253 VMIVME-7697 Product Manual /* get watchdog base address from config area */ test_int = read_configuration_area(READ_CONFIG_DWORD, bus, dev_func, 0x24, &temp_dword); if(test_int != SUCCESSFUL) printf(“\nUnable to read WATCHDOG BASE ADDRESS @ 0x24 in config space\n”); exit( 1 ); wd_base = temp_dword & 0xFFFFFFF0;...
  • Page 254 Directory WATCHDOG test_int = fr_byte( wd_base + WD_MSEC); fw_byte( wd_base + 0x40, 0x00 ); /* disable watchdog in EPLD */ /* set WatchDog Alarm Mask 1 - deactivated and update with 0 time */ fw_byte( wd_base + WD_CMD, ( WD_TE | WD_WAM ) ); fw_byte( wd_base + WD_MSEC, 0 );...

  • Page 255: File: Wd_Sf.c

    VMIVME-7697 Product Manual ** FILE: WD_SF.C #include <stdlib.h> #include <stdio.h> #include <dos.h> #include <time.h> #include <conio.h> #include <ctype.h> #include “watchdog.h” #include “flat.h” #include “pci.h” #define DID_7697 0x7697 /* Device ID #define VID_7697 0x114A /* Vendor ID /* global variables */ unsigned char bus, dev_func;...
  • Page 256 Directory WATCHDOG printf(“\nUnable to locate 7697\n”); exit( 1 ); /* get watchdog base address from config area */ test_int = read_configuration_area(READ_CONFIG_DWORD, bus, dev_func, 0x24, &temp_dword); if(test_int != SUCCESSFUL) printf(“\nUnable to read WATCHDOG BASE ADDRESS @ 0x24 in config space\n”); exit( 1 ); wd_base = temp_dword &...
  • Page 257 VMIVME-7697 Product Manual fw_byte( wd_base + WD_MSEC, 0x00 ); /* 00.00 seconds */ fw_byte( wd_base + WD_SEC, 0x10 ); /* 10.00 seconds */ fw_byte( wd_base + WD_CMD, WD_TE ); delay( 10000 ); /* the sys fail LED should be on */ while( !kbhit() );...
  • Page 258 Index Numerics 100BaseTX Ethernet 56, 89 10BaseT controller Digital Semiconductor’s 21143 controller interrupt logic LED definition Windows 95 setup address map Windows for Workgroups (V3.11) auxiliary I/O mapping Windows NT (Version 4.0) Expansion ROM Read Enable Register 41, 52, 148 BIOS BIOS FEATURES SETUP Floppy Disk Drive...
  • Page 259 VMIVME-7697 Product Manual Intel 21143 68, 70 Intel 82C54 interrupt lines Intel programmers local bus interrupt line assignment PCI bus interrupt vector table PCI Configuration Space Registers 17, 20 IOWorks Access PCI host bridge ISA bus PCI IDE controller ISA device interrupt mapping...
  • Page 260 Index synchronous negotiation synchronous transfer rate System BIOS Setup Utility terminators Timer Address Map Comparison Table configuration Control circuitry sets Mode Register Values Width Bit Field Timer 2 width Timer Block Diagram timer control unpacking procedures Upper Counter USB interrupt mapping USB port connector vector interrupt table verifying disks...
  • Page 261 VMIVME-7697 Product Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
  • Page 262 Artisan Technology Group is your source for quality new and certified-used/pre-owned equipment SERVICE CENTER REPAIRS WE BUY USED EQUIPMENT • FAST SHIPPING AND DELIVERY Experienced engineers and technicians on staff Sell your excess, underutilized, and idle used equipment at our full-service, in-house repair center We also offer credit for buy-backs and trade-ins •...

Table of Contents