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VMIC VMIVME-7740 Product Manual

Single board pentium iii processor-based vmebus sbc
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VMIVME-7740
Single Board Pentium III Processor-Based VMEbus SBC
Product Manual
12090 South Memorial Parkway
Huntsville, Alabama 35803-3308, USA
w
w
500-007740-000 Rev. A
(256) 880-0444
(800) 322-3616
Fax: (256) 882-0859

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  • Page 1 VMIVME-7740 Single Board Pentium III Processor-Based VMEbus SBC Product Manual 12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA 500-007740-000 Rev. A (256) 880-0444 (800) 322-3616 Fax: (256) 882-0859...
  • Page 2 12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA (256) 880-0444 (800) 322-3616 Fax: (256) 882-0859...
  • Page 3 VMIC reserves the right to make any changes, without notice, to this or any of VMIC’s products to improve reliability, performance, function, or design. VMIC does not assume any liability arising out of the application or use of any product or circuit described herein; nor does VMIC convey any license under its patent rights or the rights of others.
  • Page 4 12090 South Memorial Parkway Huntsville, Alabama 35803-3308, USA (256) 880-0444 (800) 322-3616 Fax: (256) 882-0859...

  • Page 5: Table Of Contents

    VMIVME-7740 Product Options ........
  • Page 6 VMIVME-7740 Product Manual PCI Interrupts ................48 I/O Ports .
  • Page 7 Table of Contents VMEbus Connector Pinout ..............84 Appendix B - System Driver Software .
  • Page 8 VMIVME-7740 Product Manual Installed O/S ................99 Reset Configuration Data .
  • Page 9 Table of Contents Data Book References ..............116 Device Address Definition .
  • Page 10 VMIVME-7740 Product Manual...
  • Page 11 Figure A-1 VMIVME-7740 Connector and Jumper Locations ....... . .
  • Page 12 VMIVME-7740 Product Manual...
  • Page 13 VMIVME-7740 I/O Address Map ........
  • Page 14 VMIVME-7740 Product Manual...

  • Page 15: Overview

    VMEbus modules via the on-board PCI-to-VMEbus bridge and the Endian conversion hardware. The VMIVME-7740 may be accessed as a VMEbus slave board. The VMEbus functions are available by programming the VMIVME-7740’s PCI-to-VMEbus bridge according to the references defined in this volume and/or in the second volume dedicated to the optional PCI-to-VMEbus interface board titled: VMIVME-7740 Tundra Universe -Based VMEbus Interface Product Manual (document No.

  • Page 16: Organization Of The Manual

    Organization of the Manual This manual is composed of the following chapters and appendices: Chapter 1 - VMIVME-7740 Features and Options describes the features of the base unit followed by descriptions of the associated features of the unit in operation on a VMEbus.

  • Page 17: References

    References References For the most up-to-date specifications for the VMIVME-7740, please refer to: VMIC specification number 800-007740-000 The following books refer to the Tundra Universe II-based interface available in the VMIVME-7740: VMIVME-7740, Tundra Universe II -Based VMEbus Interface Product Manual ™...
  • Page 18 VMIVME-7740 Product Manual For a detailed description and specification of the VMEbus, please refer to: VMEbus Specification Rev. C.1 and The VMEbus Handbook VMEbus International Trade Association (VITA) 7825 East Gelding Dr. Suite No. 104 Scottsdale, AZ 85260 (602) 951-8866 FAX: (602) 951-0720 www.vita.com...

  • Page 19: Safety Summary

    Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design, manufacture, and intended use of this product. VMIC assumes no liability for the customer’s failure to comply with these requirements. Ground the System To minimize shock hazard, the chassis and system cabinet must be connected to an electrical ground.

  • Page 20: Safety Symbols Used In This Manual

    VMIVME-7740 Product Manual Safety Symbols Used in This Manual Indicates dangerous voltage (terminals fed from the interior by voltage exceeding 1000 V are so marked). Protective conductor terminal. For protection against electrical shock in case of a fault. Used with field wiring terminals to indicate the terminal which must be connected to ground before operating equipment.

  • Page 21: Notation And Terminology

    Notation and Terminology Notation and Terminology This product bridges the traditionally divergent worlds of Intel-based PC’s and Motorola-based VMEbus controllers; therefore, some confusion over “conventional” notation and terminology may exist. Every effort has been made to make this manual consistent by adhering to conventions typical for the Motorola/VMEbus world; nevertheless, users in both camps should review the following notes: •...
  • Page 22 VMIVME-7740 Product Manual...

  • Page 23: Chapter 1 - Vmivme-7740 Features And Options

    VMEbus Features ........... . 26 Introduction The VMIVME-7740 performs all the functions of a standard IBM PC/AT motherboard with the following features: •...

  • Page 24: Table 1-1 Pc/At I/O Features

    VMIVME-7740 Product Manual The VMIVME-7740 supports standard PC/AT I/O features such as those listed in Table 1-1. Figure 1-1 on page 25 shows a block diagram of the VMIVME-7740 emphasizing the I/O features including the PCI-to-VMEbus bridge. Table 1-1 PC/AT I/O Features...

  • Page 25: Figure 1-1 Vmivme-7740 Block Diagram

    Accelerator Universe IIB (PIIX4E) COM Port 1 CF Socket P7 EIDE Hard COM Port 2 Drive SUPER with Flash BIOS 16-bit Timers Floppy Drive 32 Kbyte NVRAM FDC37C67X Watchdog Timer NVRAM Controller DS1384 PS/2 Keyboard/Mouse Figure 1-1 VMIVME-7740 Block Diagram...

  • Page 26: Vmebus Features

    VMIVME-7740 Product Manual VMEbus Features In addition to its PC/AT functions, the VMIVME-7740 has the following VMEbus features: • Single-slot, 6U height VMEbus board • Complete six-line Address Modifier (AM-Code) programmability • VME data interface with separate hardware byte/word swapping for master and slave accesses •...

  • Page 27: Vmivme-7740 Product Options

    These involve processor performance, the Flash Disk, and SDRAM memory size. These options are subject to change based on emerging technologies and availability of vendor configurations. The options and current details available with the VMIVME-7740 are defined in the device specification sheet available from your VMIC representative.
  • Page 28 VMIVME-7740 Product Manual...

  • Page 29: Chapter 2 - Installation And Setup

    All claims arising from shipping damage should be filed with the carrier and a complete report sent to VMIC Customer Service together with a request for advice concerning the disposition of the damaged item(s).

  • Page 30: Hardware Setup

    VMIVME-7740 Product Manual Hardware Setup The VMIVME-7740 is factory populated with user-specified options as part of the VMIVME-7740 ordering information. The CPU speed, SDRAM, and flash size are not user-upgradable. To change these options contact customer service to receive a Return Material Authorization (RMA).

  • Page 31: Figure 2-1 Vmivme-7740 Cpu Board, I/O Port

    Hardware Setup 10BaseT/ 100 Base Tx LAN 1 10BaseT/ 100 Base Tx LAN 2 Sysfail/HD/+5 V PWR THERM Indicator COM 1 COM 2 Reset Keyboard/Mouse SVGA Port Figure 2-1 VMIVME-7740 CPU Board, I/O Port, and Jumper Locations...

  • Page 32: Table 2-1 Cpu Board Connectors

    USB Connectors E9/E7/E11/E12 Factory Use Only Jumper E8 below serves several functions on the VMIVME-7740. These functions are: The Watchdog Timer/NMI, Programmable Timer Clock Select, and the NVRAM Battery Enable. Table 2-2 Timers and NVRAM Battery Select (User Configurable) - Jumper (E8)

  • Page 33: Table 2-5 Cmos Battery Enable - Jumper (E10)

    Normal Boot Block Programming NOTE: The VMIVME-7740’s BIOS has the capability (Default: Disabled) of password protecting casual access to the unit’s CMOS set-up screens. The Password Clear jumper (E4) allows for a means to clear the password feature, as might be necessary to do in the case of a forgotten password.

  • Page 34: Table 2-6 Vme Interface Jumper Options And Factory Settings (E13, E14)

    VMIVME-7740 Product Manual Table 2-6 VME Interface Jumper Options and Factory Settings (E13, E14) Jumper Function Jumper Position E13, 1-3 Installed - Universe Memory Mapped Installed (should not be removed) E13, 2-4 Installed - SYSFAIL Not Asserted Upon Reset Installed...

  • Page 35: Installation

    VMIVME-7740 installation and power-up: 1. Make sure power to the equipment is off. 2. Choose chassis slot. The VMIVME-7740 must be attached to a dual P1/P2 VMEbus backplane. If the VMIVME-7740 is to be the VMEbus system controller, choose the first VMEbus slot.

  • Page 36: Bios Setup

    The CMOS configuration controls many details concerning the behavior of the hardware from the moment power is applied. The VMIVME-7740 is shipped from the factory with no hard drives configured in CMOS. The BIOS Setup program must be run to configure the specific drives attached.

  • Page 37: Led Definition

    Installation LED Definition LED 1 Therm - (Red) Indicates when the CPU Temperature Throttle is active. VMIVME 7740 LED 2 Power - (Grn)Indicates when 10BaseT/ power is applied to the board. 100BaseTx LAN 1 LED 3 Hard Drive Indicator - (Yel) Indicates when hard drive activity is occurring.
  • Page 38 VMIVME-7740 Product Manual...

  • Page 39: Chapter 3 - Pc/At Functions

    Because the design is PC/AT compatible, it retains standard PC memory and I/O maps along with standard interrupt architecture. Furthermore, the VMIVME-7740 includes Ethernet controllers, an AGP-compatible video adapter, and a USB controller. The following sections describe in detail the PC/AT functions of the VMIVME-7740.

  • Page 40: Cpu Socket

    III processor. The CPU speed and SDRAM size are user-specified as part of the VMIVME-7740 ordering information. The options are not user-upgradable. To change CPU speeds or RAM size, contact VMIC customer service to obtain a Return Material Authorization (RMA).

  • Page 41: Memory And Port Maps

    Memory and Port Maps Memory Map The memory map for the VMIVME-7740 is shown in Table 3-1. All systems share this same memory map, although a VMIVME-7740 with less than the full 512 Mbyte of SDRAM does not fill the entire space reserved for On-Board Extended Memory.

  • Page 42: I/O Port Map

    The BIOS initializes and configures all these registers properly; adjusting these I/O ports directly is not normally necessary. The assigned and user-available I/O addresses are summarized in the I/O Address Map, Table 3-2. Table 3-2 VMIVME-7740 I/O Address Map I/O ADDRESS SIZE IN HW DEVICE...
  • Page 43 Programmable Internal Timer $504 - $CFF Reserved * While these I/O ports are reserved for the listed functions, they are not implemented on the VMIVME-7740. They are listed here to make the user aware of the standard PC/AT usage of these ports.

  • Page 44: Pc/At Interrupts

    The interrupt number in HEX and decimal are also defined for real and protected mode in Table 3-4. The interrupt hardware implementation on the VMIVME-7740 is standard for computers built around the PC/AT architecture, which evolved from the IBM PC/XT.

  • Page 45: Table 3-4 Pc/At Interrupt Vector Table

    PC/AT Interrupts Table 3-3 PC/AT Hardware Interrupt Line Assignments (Continued) AT FUNCTION COMMENTS Not Assigned Determined by BIOS Not Assigned Determined by BIOS Mouse Math Coprocessor AT Hard Drive Flash Drive Table 3-4 PC/AT Interrupt Vector Table INTERRUPT NO. REAL MODE PROTECTED MODE LINE Divide Error...
  • Page 46 VMIVME-7740 Product Manual Table 3-4 PC/AT Interrupt Vector Table (Continued) INTERRUPT NO. REAL MODE PROTECTED MODE LINE BIOS Video I/O Coprocessor Error Eqpt Configuration Check Same as Real Mode Memory Size Check Same as Real Mode XT Floppy/Hard Drive Same as Real Mode...
  • Page 47 PC/AT Interrupts Table 3-4 PC/AT Interrupt Vector Table (Continued) INTERRUPT NO. REAL MODE PROTECTED MODE LINE DOS 3.x+ Network Comm Same as Real Mode DOS Internal Use Same as Real Mode DOS Internal Use Same as Real Mode DOS Internal Use Same as Real Mode DOS Internal Use Same as Real Mode...

  • Page 48: Pci Interrupts

    For a single function device, only INTA# may be used while the other three interrupt lines have no meaning. Figure 3-1 on page 49 depicts the VMIVME-7740 interrupt logic pertaining to VMEbus operations and the PCI expansion site.

  • Page 49: I/O Ports

    I/O Ports I/O Ports The VMIVME-7740 incorporates the SMC Super-I/O chip. The SMC chip provides the VMIVME-7740 with a standard floppy drive controller and two 16550 UART-compatible serial ports. The Ultra-IDE hard drive interface is provided by the Intel 82371EB (PIIX4E) PCI ISA IDE Xcelerator chip. All ports are present in their standard PC/AT locations using default interrupts.

  • Page 50: Video Graphics Adapter

    VMIVME-7740 Product Manual Video Graphics Adapter The monitor port on the VMIVME-7740 is controlled by a Chips and Technology 69030 video adapter chip with 4 Mbyte embedded video SDRAM. The video controller chip is hardware and BIOS compatible with the IBM EGA and SVGA standards and also supports VESA high-resolution and extended video modes.

  • Page 51: Ethernet Controllers

    10BaseT has a maximum length of 100 m from the wiring hub to the terminal node. 100BaseTx The VMIVME-7740 also supports the 100BaseTx Ethernet. A network based on a 100BaseTx standard uses unshielded twisted-pair cables and a RJ-45 connector. The 100BaseTx has a maximum deployment length of 250 m.
  • Page 52 VMIVME-7740 Product Manual...

  • Page 53: Chapter 4 - Embedded Pc/Rtos Features

    Watchdog Timer for synchronizing and controlling multiple events in embedded applications. The VMIVME-7740 also provides a bootable Flash Disk system and 32 K byte of NVRAM. These features make the unit ideal for embedded applications, particularly...

  • Page 54: Timers

    VMIVME-7740 Product Manual Timers General The VMIVME-7740 provides a user-programmable 82C54 internal timer/counter. The 82C54 provides three independent, 16-bit timers, each operating at 1 or 2 MHz clock speed determined by the configuration of jumper E8; reference Table 2-2 on page 32.

  • Page 55: Clearing The Interrupt

    Timer Programming Architecture The VMIVME-7740 Timers are mapped in I/O address space starting at $500 (see Table 4-1). The Timers, consisting of three 16-bit timers and a Control Word Register (see Figure 4-4) are read from/written to via an 8-bit data bus.
  • Page 56 VMIVME-7740 Product Manual Table 4-1 shows the I/O addresses of the Control Word Register and Timers. The Control Word Register is write only. The Timer status information can be obtained from the Read-Back command (see the “Reading” section on page 59).

  • Page 57: Writing

    Timers There are two 8-bit registers labeled TR and TR (Timer Register). The subscripts M and L stand for Most Significant byte and Least Significant byte. When a new count is written to the Timer, the count is loaded into the TR and later transferred to the TE. The Control logic lets one 8-bit TR register be written to at a time.

  • Page 58: Table 4-3 St - Select Timer

    VMIVME-7740 Product Manual Table 4-3 ST - Select Timer ST1* ST0* Description Select Timer 0 Select Timer 1 Select Timer 2 Read-Back Command (See Reading section on page 59) *The ST bits specify which Timer (0, 1, or 2) the Control word refers to or whether this is a Read-Back command.

  • Page 59: Reading

    Timers Table 4-6 BCD BCD* Description Binary Timer 16-bits Binary Coded Decimal (BCD) Timer (4 Decades) * The BCD bit specifies whether the Timer count value is in Binary or BCD. When programming the 82C54, only two rules need to be followed. 1.

  • Page 60: Table 4-6 Bcd

    VMIVME-7740 Product Manual Read-Back Command The Read-Back Command allows the user to view the Timer Count, the Timer Mode, the current state of the OUT pin, and the Load Flag of the selected Timer. Like a Control Word, the Read-Back Command is written into the Control Word Register and has the format shown in Tables 4-7 and 4-8.

  • Page 61: Table 4-10 Status Byte Description

    Timers Table 4-10 Status Byte Description Description D7: OUT Current state of Timers OUT pin D6: LOAD Count loaded into Timer D5-D0 Timer Programmed Mode Bit D7 contains the state of the Timers OUT pin. This allows viewing of the Timer’s OUT pin via software.

  • Page 62: Mode Definitions

    The VMIVME-7740 utilizes an 82C54 Timer/Counter for its Timers. 82C54 Timer/Counters can be programmed to function in six different modes (numbered Mode 0 through Mode 5). The VMIVME-7740 Timers are hardware configured to operate using Mode 2. Only Mode 2 is defined.

  • Page 63: Flash Disk

    Configuration The Flash Disk resides on the VMIVME-7740 as the secondary IDE bus master device (the secondary IDE bus slave device is not assignable). The default setting is AUTO. This can be seen in the BIOS menus. From the Main BIOS menu select Secondary Master and press the Enter key.

  • Page 64: Functionality

    Some applications may require the use of multiple partitions. The following discussion of partitions includes the special procedures that must be followed to allow the creation of multiple partitions on the VMIVME-7740 IDE disk devices (including the resident Flash Disk).
  • Page 65 Flash Disk 2. Set Primary Master to None. Set Secondary Master to Auto. Set boot device to floppy. 3. Boot DOS from the floppy; verify, on the Bootup screen, that the Flask Disk is shown as Flash Disk 0. 4. Run FDISK. 5.
  • Page 66 VMIVME-7740 Product Manual system will continue to assign drive letters to the primary partitions in an alternating fashion between the two drives. Next, logical partitions will be assigned drive letters starting on the first hard drive lettering each logical device sequentially until they are all named, then doing the same sequential lettering of each logical partition on the second hard disk.

  • Page 67: Watchdog Timer

    Non-Volatile SRAM controller. The Time of Day feature found within the DS1384 device is explained in this section, but is not utilized by the VMIVME-7740. The actual Time of Day registers used by the VMIVME-7740 are located at the standard PC/AT I/O address.

  • Page 68: Table 4-12 Watchdog Registers

    VMIVME-7740 Product Manual Table 4-12 Watchdog Registers Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Range $D8000 0.1 Seconds (BCD) 0.01 Seconds (BCD) 00 - 99 $D8001 10 Seconds (BCD)

  • Page 69: Time Of Day Registers

    Watchdog Timer Time of Day Registers Registers 0, 1, 2, 4, 6, 8, 9, and A contain Time of Day data in BCD. Register 0 contains two Time of Day values. Bits 3 - 0 contain the 0.01 Seconds value with a range of 0 to 9 in BCD while Bits 7 - 4 contain the 0.1 Seconds value with a range of 0 to 9 in BCD.

  • Page 70: Time Of Day Alarm Registers

    VMIVME-7740 Product Manual There are two techniques for reading the Time of Day from the Watchdog Timer. The first is to halt the external Time of Day registers from tracking the internal Time of Day registers by setting the Te bit (Bit 7 of the Command Register) to a logic zero (0), then reading the contents of the Time of Day registers.

  • Page 71: Watchdog Alarm Registers

    Watchdog Timer Watchdog Alarm Registers Register C contains two Watchdog Alarm values. Bits 3 - 0 contain the 0.01 Seconds value with a range of 0 to 9 in BCD, while Bits 7 - 4 contain the 0.1 Seconds value with a range of 0 to 9 in BCD.
  • Page 72 VMIVME-7740 Product Manual Tdm - Bit 2 Time of Day Alarm Mask - Enables/Disables the Time of Day Alarm to Interrupt Output when Ipsw (see Bit 6, Interrupt Switch) is set to logic one (1). When set to a logic zero (0), Time of Day Alarm Interrupt Output will be enabled. When set to a logic one (1), Time of Day Alarm Interrupt Output will be disabled.

  • Page 73: Nvram

    NVRAM NVRAM The VMIVME-7740 includes 32 K bytes of NVRAM addressed at $D8018 to $DFFFF. The lower 24 bytes, $D8000 to $D8017, are dedicated to the Watchdog Timer, the System Command Register, the VME BERR Address Register, the VME BERR Address Modifier Register and the Board ID Register and are unavailable for SRAM use.
  • Page 74 VMIVME-7740 Product Manual...

  • Page 75: Chapter 5 - Maintenance

    8. Quality of cables and I/O connections If products must be returned, obtain a RMA (Return Material Authorization) by contacting VMIC Customer Service. This RMA must be obtained prior to any return. VMIC Customer Service is available at: 1-800-240-7782. Or E-mail us at customer.service@vmic.com Maintenance Prints User level repairs are not recommended.
  • Page 76 VMIVME-7740 Product Manual...

  • Page 77: Appendix A - Connector Pinouts

    The VMIVME-7740 PC/AT-Compatible VMEbus Controller has several connectors for its I/O ports. Figure A-1 shows the locations of the connectors on the VMIVME-7740. Wherever possible, the VMIVME-7740 uses connectors and pinouts typical for any desktop PC. This ensures maximum compatibility with a variety of systems.

  • Page 78: Figure A-1 Vmivme-7740 Connector And Jumper Locations

    VMIVME-7740 Product Manual 10BaseT/ 100 Base Tx LAN 1 10BaseT/ 100 Base Tx LAN 2 Sysfail/HD/+5 V PWR THERM Indicator COM 1 COM 2 Reset Keyboard/Mouse SVGA Port Figure A-1 VMIVME-7740 Connector and Jumper Locations...

  • Page 79: Dual Ethernet Connectors Pinout (J1, J7)

    Dual Ethernet Connectors Pinout (J1, J7) Dual Ethernet Connectors Pinout (J1, J7) The pinout diagram for the Ethernet 10BaseT/100BaseTx connectors is shown in Figure A-2. ETHERNET CONNECTOR 10BaseT/100BaseTx Signal Name Transmit Data Transmit Data Receive Data TX_CT_OUT Transmit Center Tap Out TX_CT_OUT Transmit Center Tap Out LAN1...

  • Page 80: Video Connector Pinout (J3)

    VMIVME-7740 Product Manual Video Connector Pinout (J3) The video port uses a standard high-density D15 SVGA connector. Figure A-3 illustrates the pinout. VIDEO CONNECTOR DIRECTION FUNCTION Green Blue Reserved Ground Ground Ground Ground Reserved Ground Reserved Reserved Horizontal Sync Vertical Sync...

  • Page 81: Serial Connector Pinout (P3)

    Serial Connector Pinout (P3) Serial Connector Pinout (P3) Each standard RS-232 serial port connector is a Microminiature D9 male as shown in the drawing in Figure A-4. Adapters to connect standard D9 serial peripherals to the board are available. Please refer to the product specification sheet for ordering information.

  • Page 82: Usb Connector (J8)

    VMIVME-7740 Product Manual USB Connector (J8) The Universal Serial Bus (USB) port uses an industry standard, four position shielded connector. Figure A-5 shows the pinout of the USB connector. Signal Function USBV USB Power USB- USB Data - Board Side...

  • Page 83: Keyboard/Mouse Connector Pinout

    The keyboard/Mouse connector is a standard 6-pin female mini-DIN PS/2 connector as shown in Figure A-6. The Keyboard/Mouse Y-cable connects to the Keyboard/Mouse connector on the VMIVME-7740 and provides a separate connector for both Keyboard and Mouse. The pinout of these connectors are shown in Table A-1.

  • Page 84: Vmebus Connector Pinout

    VMIVME-7740 Product Manual VMEbus Connector Pinout Figure A-7 shows the location of the VMEbus P1 and P2 connectors and their orientation. Table A-2 and Table A-3 show the pin assignments for the VMEbus connectors. Figure A-7 VME64 Connector Diagram Table A-2 P1 - VME64 Connector...
  • Page 85 VMEbus Connector Pinout Table A-2 P1 - VME64 Connector (Continued) Signal Description Signal Description N.C. No Connect N.C. No Connect N.C. No Connect N.C. No Connect N.C. No Connect N.C. No Connect N.C. No Connect N.C. No Connect N.C. No Connect N.C.

  • Page 86: Table A-3 P2 - Vme64 Connector

    VMIVME-7740 Product Manual Table A-3 P2 - VME64 Connector Signal Description Signal Description Signal Description Ground Power IDERST# IDE Control IDED[8] IDE Data Line 8 Ground IDED[7] IDE Data Line 7 IDED[9] IDE Data Line 9 N.C. No Connect IDED[6]...
  • Page 87 VMEbus Connector Pinout Table A-3 P2 - VME64 Connector (Continued) Signal Description Z Signal Description CONN[1] P8-2 CONN[2] P8-2 CONN[3] P8-3 Ground CONN[4] P8-4 CONN[5] P8-5 CONN[6] P8-6 Ground CONN[7] P8-7 CONN[8] P8-8 CONN[9] P8-9 Ground 7 CONN[10] P8-10 7 CONN[11] P8-11 8 CONN[12] P8-12...
  • Page 88 VMIVME-7740 Product Manual...

  • Page 89: Appendix B - System Driver Software

    Driver Software Installation In order to properly use the Video and LAN adapters of the VMIVME-7740, the user must install the driver software located on the distribution diskettes provided with the unit. Detailed instructions for installation of the drivers during installation of Windows 98 or Windows NT (Versions 4.0) operating systems are described in the...

  • Page 90: Windows 98 Se (Second Edition)

    VMIVME-7740 Product Manual Windows 98 SE (Second Edition) 1. Begin installation of Windows 98 SE, following the instructions provided by the Windows 98 SE manual. 2. When you reach the ‘WINDOWS 98 SE SETUP WIZARD SCREEN’, choose ‘TYPICAL’ under ‘SETUP OPTIONS’ and then click ‘NEXT’.

  • Page 91: Windows Nt (Version 4.0)

    Windows NT (Version 4.0) Windows NT (Version 4.0) Windows NT 4.0 includes drivers for the on-board LAN, and video adapters. The following steps are required to configure the LAN for operation. 1. Follow the normal Windows NT 4.0 installation until you reach the Windows NT Workstation Setup window which states that Windows NT Needs To Know How This Computer Should Participate On A Network.
  • Page 92 VMIVME-7740 Product Manual 20. Select the Settings tab in the Display Properties window, then click the Display Type button. 21. In the Display Type window, click Change. 22. In the Change Display window, click Have Disk. 23. Insert disk 320-500052-002 into drive A.

  • Page 93: Appendix C - Phoenix Bios

    Exit Menu ............106 Introduction The VMIVME-7740 utilizes the BIOS (Basic Input/Output System) in the same manner as other PC/AT compatible computers. This appendix describes the menus and options associated with the VMIVME-7740 BIOS.

  • Page 94: Main Menu

    VMIVME-7740 Product Manual Main Menu The Main menu allows the user to select QuickBoot, set the system clock and calendar, record disk drive parameters, and set selected functions for the keyboard. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ H6DI 6q‰hprq Q‚r… Trpˆ…v‡’ 7‚‚‡ @‘v‡ D‡r€ÃTƒrpvsvpÃCryƒ Rˆvpx7‚‚‡ÃH‚qr) b@hiyrqd...

  • Page 95: Legacy Diskette

    The VMIVME-7740 does not support a second floppy drive. The default is Disabled. Primary Master/Slave The VMIVME-7740 has the capability of utilizing one IDE hard disk drive on the Primary Master bus. The default setting is Auto. The Primary Slave is assigned to the CD-ROM (if installed).

  • Page 96: Secondary Master

    VMIVME-7740 Product Manual Secondary Master The Secondary Master is the resident Flash Disk (if installed). The default setting is Auto. Keyboard Features The Keyboard Features allows the user to set several keyboard functions. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ H6DI D‡r€ÃTƒrpvsvpÃCryƒ Fr’i‚h…qÃArh‡ˆ…r† Tryrp‡†ÃQ‚r…‚Ã†‡h‡r Iˆ€G‚px) b6ˆ‡‚d s‚…ÃIˆ€G‚px...

  • Page 97: Keyboard Auto-Repeat Delay (Sec)

    Main Menu Keyboard Auto-Repeat Delay (sec) If the Key Click is enabled, this determines the delay before a character starts repeating when a key is held down. The options are: 1/4, 1/2, 3/4, or 1 second. The default is 1/2. Keyboard Test When enabled, this feature will test the keyboard during boot-up.

  • Page 98: Com Port Address

    VMIVME-7740 Product Manual Com Port Address If enabled, it will allow remote access through the serial port. The options are: Disabled, Motherboard Com A, and Motherboard Com B. The default is Disabled. Baud Rate Selects a baud rate for the serial port. The options are: 600, 1200, 2400, 4800, 9600, 19.2, 38.4, and 115.2.

  • Page 99: Advanced Menu

    Advanced Menu Advanced Menu Selecting Advanced from the Main menu will display the screen shown below. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ H6DI 6q‰hprq Q‚r… Trpˆ…v‡’ 7‚‚‡ @‘v‡ D‡r€ÃTƒrpvsvpÃCryƒ D†‡hyyrqÃPT) bP‡ur…d @hiyrÃ68QD) bI‚d Tryrp‡Ã‡urƒr…h‡vt Sr†r‡Ã8‚svtˆ…h‡v‚Ã9h‡h) bI‚d †’†‡r€Ãv†‡hyyrq # 8hpurÃHr€‚…’ ‚Ã’‚ˆ…Æ’†‡r€Ãuvpu # DPÃ9r‰vprÃ8‚svtˆ…h‡v‚ ’‚ˆÃvyyȆrÀ‚†‡ Gh…trÃ9v†xÃ6ppr††ÃH‚qr) b9PTd p‚€€‚y’ G‚phyÃ7ˆ†ÃD9@Ãhqhƒ‡r…) b7‚‡ud...

  • Page 100: I/O Device Configuration

    VMIVME-7740 Product Manual Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ 69W6I8@9 D‡r€ÃTƒrpvsvpÃCryƒ 8hpurÃHr€‚…’ Tr‡†Ã‡urƇh‡rÂsÇur Hr€‚…’Ã8hpur) b@hiyrqd €r€‚…’Ãphpur 8hpurÃT’†‡r€Ã7DPTÃh…rh) bX…v‡rÃQ…‚‡rp‡d 8hpurÃWvqr‚Ã7DPTÃh…rh) bX…v‡rÃQ…‚‡rp‡d 8hpurÃ7h†rÃ$ !x) bX…v‡rÃ7hpxd 8hpurÃ7h†rÃ$ !x%#x) bX…v‡rÃ7hpxd 8hpurÃ@‘‡rqrqÃHr€‚…’Ã6…rh) bX…v‡rÃ7hpxd 8hpurÃ66AAA) b9v†hiyrqd 8hpurÃ77AAA) b9v†hiyrqd 8'87AA) b9v†hiyrqd 888AAA) b9v†hiyrqd 99"AA) b9v†hiyrqd 9#9&AA) b9v†hiyrqd 9'97AA) b9v†hiyrqd 989AAA) b9v†hiyrqd @@"AA) b9v†hiyrqd...

  • Page 101: Large Disk Access Mode

    Advanced Menu Large Disk Access Mode The options for the Large Disk Access Mode are: UNIX Novell Netware or Other. If you are installing new software and the drive fails, change this selection and try again. Different operating systems require different representations of drive geometries.

  • Page 102: Enable Memory Map

    VMIVME-7740 Product Manual Enable Memory Map If enabled, turn system RAM off to free address space for use with an option card. Either a 128KB conventional memory gap, starting at 512KB, or a 1MB extended memory gap, starting at 15MB, will be created in the system RAM. The options are Disabled, Conventional, or Extended.

  • Page 103: Power

    Power Power This screen, selected from the Main screen, allows the user to configure power saving options on the VMIVME-7740. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ H6DI 6q‰hprq Q‚r… Trpˆ…v‡’ 7‚‚‡ @‘v‡ D‡r€ÃTƒrpvsvpÃCryƒ Q‚r…ÃTh‰vt†) b9v†hiyrqd Hh‘v€ˆ€ÃQ‚r…Æh‰vt† 8QVÃUu…‚‡‡yvtÃ9‚ÃUu…r†u‚yq) b9v†hiyrqd p‚†r…‰r†Ã‡urÃt…rh‡r†‡ h€‚ˆ‡Ã‚sÆ’†‡r€Ãƒ‚r… T‡hqi’ÃUv€r‚ˆ‡) bPssd Hh‘v€ˆ€ÃQr…s‚…€hpr 6ˆ‡‚ÃTˆ†ƒrqÃUv€r‚ˆ‡) bPssd p‚†r…‰r†Ãƒ‚r…Ãiˆ‡...

  • Page 104: Security

    VMIVME-7740 Product Manual Security Utilize this screen to set a user password. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ Trpˆ…v‡’ D‡r€ÃTƒrpvsvpÃCryƒ Trpˆ…v‡’ Tˆƒr…‰v†‚…ÃQh††‚…q Tr‡ÃTˆƒr…‰v†‚…ÃQh††‚…q bà @‡r… Ãd p‚‡…‚y†Ã6ppr††Ã‡‚Çur †r‡ˆƒÃˆ‡vyv‡’ Tr‡Ã Tˆƒr…‰v†‚…à Qh††‚…qà à à @‡r…ÃIrÃQh††‚…q bÃÃÃÃÃÃÃd 8‚sv…€ÃIrÃQh††‚…q bÃÃÃÃÃÃÃd A Cryƒ Tryrp‡ÃD‡r€8uhtrÃWhyˆr†A(Tr‡ˆƒÃ9rshˆy‡† ↑ ↓ @T8@‘v‡ Tryrp‡ÃHrˆ@‡r…Tryrp‡Ã#ÃTˆiHrˆA Th‰rÃhqÃ@‘v‡...

  • Page 105: Boot Menu

    Boot Menu Boot Menu The Boot priority is determined by the stack order, with the top having the highest priority and the bottom the least. The order can be modified by highlighting a device and, using the <+> or <-> keys, moving it to the desired order in the stack. A device can be boot disabled by highlighting the particular device and pressing <Shift 1>.

  • Page 106: Exit Menu

    VMIVME-7740 Product Manual Exit Menu The Exit menu allows the user to exit the BIOS program, while either saving or discarding any changes. This menu also allows the user to restore the BIOS defaults if desired. Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ @‘v‡ H6DI 6q‰hprq Q‚r…...

  • Page 107: Appendix D - Lanworks Bios

    BIOS Features Setup ..........110 Introduction The VMIVME-7740 includes a LANWorks option which allows the VMIVME-7740 to be booted from a network. This appendix describes the procedures to enable this...

  • Page 108: Boot Menus

    First Boot menu. Selecting “Managed PC Boot Agent (MBA)” to boot from the LAN in this screen applies to the current boot only, at the next reboot the VMIVME-7740 will revert back to the setting in the Boot menu.
  • Page 109 Boot Menus Qu‚rv‘ÃTr‡ˆƒÃV‡vyv‡’ H6DI 6q‰hprq Trpˆ…v‡’ Q‚r… 7‚‚‡ @‘v‡ D‡r€ÃTƒrpvsvpÃCryƒ HhhtrqÃQ8Ã7‚‚‡Ã6tr‡ÃH76 ÃSr€‚‰hiyrÃ9r‰vpr†) Fr’†Ãˆ†rqÇ‚ÉvrÃ‚… ÃCh…qÃ9…v‰r p‚svtˆ…rÃqr‰vpr†) ÃÃ6U6QDÃ89SPHÃ9…v‰r 1@‡r…3Ãr‘ƒhq†Ã‚… ÃSr€‚‰hiyrÃ9r‰vpr†) p‚yyhƒ†r†Ãqr‰vpr†Ãv‡u hÃÂ…Ã 18‡…yÃÃ@‡r…3Ãr‘ƒhq† hyy 1Tuvs‡Ãà 3Ãrhiyr†Ã‚… qv†hiyr†ÃhÃqr‰vpr 13ÃhqÃ13À‚‰r†Ã‡urà qr‰vprȃÂ…Ãq‚ 13Àh’À‚‰rÃ…r€‚‰hiyr qr‰vprÃir‡rrÃCh…qà 9v†xÂ…ÃSr€‚‰hiyrÃ9v†x 1q3Ã…r€‚‰rÃhÃqr‰vpr ‡uh‡Ãv†Ã‚‡Ãv†‡hyyrq A Cryƒ Tryrp‡ÃD‡r€8uhtrÃWhyˆr†A(Tr‡ˆƒÃ9rshˆy‡† ↑ ↓ @T8@‘v‡ Tryrp‡ÃHrˆ@‡r…Tryrp‡Ã#ÃTˆiHrˆA Th‰rÃhqÃ@‘v‡ ←...

  • Page 110: Bios Features Setup

    VMIVME-7740 Product Manual BIOS Features Setup After the Managed PC Boot Agent has been enabled there are several boot options available to the user. These options are RPL (default), TCP/IP, Netware, and PXE. The screens below show the defaults for each boot method.

  • Page 111: Netware

    BIOS Features Setup Netware HhhtrqÃQ8Ã7‚‚‡Ã6tr‡ÃH76É"!Ã7DPTÃD‡rt…h‡rq pÃ8‚ƒ’…vtu‡Ã (('ÃG6IX‚…x†ÃUrpu‚y‚tvr†Ã8‚Ãhƈi†vqvh…’ÂsÃ"8‚€Ã8‚…ƒ‚…h‡v‚ 6yyÃ…vtu‡†Ã…r†r…‰rq 8‚svtˆ…h‡v‚ 7‚‚‡ÃHr‡u‚q) Ir‡h…r Q…‚‡‚p‚y '!! 8‚svtÃHr††htr) @hiyrq Hr††htrÃUv€r‚ˆ‡) %ÃTrp‚q† 7‚‚‡Ãshvyˆ…rÃQ…‚€ƒ‡) Xhv‡Ãs‚…Ãxr’ 7‚‚‡ÃAhvyˆ…r) Ir‘‡Ã77TÃqr‰vpr V†rÃpˆ…†‚…Ãxr’†Ã‡‚Ãrqv‡)ÃVƒ9‚ÃpuhtrÃsvryqÃGrs‡Svtu‡ÃpuhtrÉhyˆr @T8ǂĈv‡ÃA(Ã…r†‡‚…rÃ…r‰v‚ˆ†Ã†r‡‡vt†ÃA Ç‚Æh‰r HhhtrqÃQ8Ã7‚‚‡Ã6tr‡ÃH76É"!Ã7DPTÃD‡rt…h‡rq pÃ8‚ƒ’…vtu‡Ã (('ÃG6IX‚…x†ÃUrpu‚y‚tvr†Ã8‚Ãhƈi†vqvh…’ÂsÃ"8‚€Ã8‚…ƒ‚…h‡v‚ 6yyÃ…vtu‡†Ã…r†r…‰rq 8‚svtˆ…h‡v‚ 7‚‚‡ÃHr‡u‚q) V†rÃpˆ…†‚…Ãxr’†Ã‡‚Ãrqv‡)ÃVƒ9‚ÃpuhtrÃsvryqÃGrs‡Svtu‡ÃpuhtrÉhyˆr @T8ǂĈv‡ÃA(Ã…r†‡‚…rÃ…r‰v‚ˆ†Ã†r‡‡vt†ÃA Ç‚Æh‰r...
  • Page 112 VMIVME-7740 Product Manual...

  • Page 113: Appendix E - Device Configuration: I/O And Interrupt Control

    This appendix provides the user with the information needed to develop custom applications for the VMIVME-7740. The CPU on the VMIVME-7740 is unique in that the BIOS cannot be removed; it must be used in the initial boot cycle. A custom application, like a revised operating system for example, can only begin to operate after the BIOS has finished initializing the CPU.

  • Page 114: Bios Operations

    BIOS and reconfigure the system, or it may accept what the BIOS initialized. BIOS Control Overview There are two areas on the VMIVME-7740 in which the user must be familiar in order to override the initial BIOS configuration: the device addresses and the device interrupts.

  • Page 115: Figure E-1 Vmivme-7740 Block Diagram

    Accelerator Universe IIB (PIIX4E) COM Port 1 CF Socket P7 EIDE Hard COM Port 2 Drive SUPER with Flash BIOS 16-bit Timers Floppy Drive 32 Kbyte NVRAM FDC37C67X Watchdog Timer NVRAM Controller DS1384 PS/2 Keyboard/Mouse Figure E-1 VMIVME-7740 Block Diagram...

  • Page 116: Data Book References

    Santa Clara, CA 95052-8119 (408) 765-8080 www.intel.com 6. VMIVME-7740 User Manuals 500-007740-000 Product Manual 500-007740-001 VMIVME-7740, Tundra Universe II-Based VMEbus Interface Product Manual 7. PCI Local Bus Specification, Rev. 2.1 PCI Special Interest Group P.O. Box 14070 Portland, OR 97214 (800) 433-5177 (U.S.)
  • Page 117 BIOS Operations 8. SMC FDC37C67X Enhanced Super I/O Controller SMC Component Products Division 300 Kennedy Dr. Hauppauge, NY 11788 (516) 435-6000 (516) 231-6004 (FAX) 9. ISA & EISA, Theory and Operation Solari, Edward Annabooks 15010 Avenue of Science, Suite 101 San Diego, CA 92128 USA ISBN 0-929392 -15-9 10.

  • Page 118: Device Address Definition

    64 Kbyte. ISA Devices The ISA devices on the VMIVME-7740 are configured by the BIOS at boot-up and adhere to the standard PC/AT architecture. They are mapped in I/O address space within standard addresses and their interrupts are mapped to standard interrupt control registers.

  • Page 119: Pci Devices

    PCI Devices PCI devices are fully configured under I/O and/or Memory address space. Table E-2 describes the PCI bus devices that are on-board the VMIVME-7740 along with each device’s configuration spectrum. The PCI bus includes three physical address spaces. As with ISA bus, PCI bus supports Memory and I/O address space, but PCI bus includes an additional Configuration address space.

  • Page 120: Device Interrupt Definition

    ISA Device Interrupt Map The VMIVME-7740 BIOS maps the IRQx lines to the appropriate device per the standard ISA architecture. Reference Figure E-2 on page 121. This initialization operation cannot be changed; however, a custom application could reroute the...

  • Page 121: Figure E-2 Bios Default Connections For The Pc Interrupt Logic Controller

    Device Interrupt Definition INTR 8259 MASTER-PORTS $020-$021 Keybd Interrupt Com 2 Timer Floppy Lpt 1 Timer Com 1 8-15 Control Not Used IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 8259 SLAVE- PORTS $0A0-$0A1 Real Tm Mouse Math IRQ2 Flash Hard Drv Clock Co-Proc...

  • Page 122: Pci Device Interrupt Map

    VMIVME-7740 Product Manual PCI Device Interrupt Map The PCI bus-based external devices include the two PCI expansion sites, the PCI-to-VMEbus bridge, and the VGA reserved connection. The default BIOS maps these external devices to the PCI Interrupt Request (PIRQx) lines of the PIIX4E. This mapping is illustrated in Figure E-2 on page 121 and is defined in Table E-3.

  • Page 123: Appendix F - Sample C Software

    Introduction This appendix provides listings of a library of sample code that the programmer may utilize to build applications. These files are provided to the VMIVME-7740 user on disk 320-500052-006, Sample Application C Code for the VMIVME-7740, included in the distribution disk set.

  • Page 124: Directory Cpu

    VMIVME-7740 Product Manual Directory CPU The code under the CPU directory sets up the universe chip with one PCI-TO-VME window and enables universe registers to be accessed from VME to allow mailbox access. CPU.C /****************************************************************************/ /* FILE: CPU.C /* Setup the universe chip with one PCI-TO-VME window and enable universe */ /* registers to be accessed from VME to allow mailbox access.
  • Page 125 Directory CPU /* function prototypes */ void far interrupt irq_rcvd( void ); void init_int( void ); void restore_orig_int( void ); void do_exit( int ); /* global variables */ unsigned char pic2_org; unsigned long mb0_msg; unsigned long mb1_msg; unsigned long mb2_msg; unsigned long mb3_msg;...
  • Page 126 VMIVME-7740 Product Manual un_regs = (FPTR) temp_dword; else printf(“Unable to read configuration area 0x10\n”); exit(1); else printf(“Unable to locate PCI device Tundra Universe\n”); exit(1); test_int = read_configuration_area(READ_CONFIG_BYTE, bus, dev_func, 0x3C, &temp_dword); if(test_int == SUCCESSFUL) int_line = temp_dword & 0xFF; else printf(“Unable to read configuration area 0x3C\n”);...
  • Page 127 Directory CPU /* 32K PCI slave window at 0x10000000 to VME A16 0x0000 user data */ fw_long( un_regs + LSI0_BS_A, PCI_BASE16); /* pci base for A16 */ fw_long(un_regs + LSI0_BD_A, (PCI_BASE16 + 0x8000)); /* 32K window */ fw_long(un_regs + LSI0_TO_A, (0x00000000 - PCI_BASE16)); fw_long(un_regs + LSI0_CTL_A, (LSI_CTL_EN | LSI_CTL_VDW_32 | LSI_CTL_VAS_16));...
  • Page 128 VMIVME-7740 Product Manual fw_long(un_regs + VSI6_CTL_A, 0); fw_long(un_regs + VSI7_CTL_A, 0); fw_long(un_regs + SLSI_A, 0); fw_long(un_regs + VRAI_CTL_A, 0); fw_long(un_regs + LINT_EN_A, 0); fw_word(CPUREGS, 0); restore_orig_int( ); a20(0); exit(xcode); } /* end do_exit */ /*******************************************************************/ /* init_int() /* purpose: Using the interrupt assigned, the original vector is */ saved and the vector to the new ISR is installed.
  • Page 129 Directory CPU /* enable interrupt 9 */ outp(0xa1, (pic2_org & 0xFD)); break; case 0xa: old_vect = getvect(IRQA); /* save vector for IRQ 10 */ setvect(IRQA, irq_rcvd); /* enable interrupt 10 */ outp(0xa1, (pic2_org & 0xFB)); break; case 0xb: old_vect = getvect(IRQB); /* save vector for IRQ 11 */ setvect(IRQB, irq_rcvd);...
  • Page 130 VMIVME-7740 Product Manual break; case 0xf: old_vect = getvect(IRQF); /* save vector for IRQ 15 */ setvect(IRQF, irq_rcvd); /* enable interrupt 15 */ outp(0xa1, (pic2_org & 0x7F)); break; } /* end switch */ fw_long(un_regs + LINT_STAT_A, 0xFFF7FF); /* clear any previous status bits */ fw_long(un_regs + LINT_MAP0_A, 0);...
  • Page 131 Directory CPU void restore_orig_int(void) disable(); outp(0xa1, pic2_org); switch( int_line ) case 0x9: setvect( IRQ9, old_vect ); break; case 0xa: setvect( IRQA, old_vect ); break; case 0xb: setvect( IRQB, old_vect ); break; case 0xc: setvect( IRQC, old_vect ); break; case 0xd: setvect( IRQD, old_vect );...
  • Page 132 VMIVME-7740 Product Manual /*******************************************************************/ /* irq_rcvd() /* purpose: Interrupt service routine. (INTA handler) /*******************************************************************/ /* parameters: none /*******************************************************************/ /* return value: none /*******************************************************************/ void interrupt irq_rcvd( void ) unsigned long lint_enable, tmp_status; disable(); asm { .386P push eax push ebx int_status = fr_long( un_regs + LINT_STAT_A );...
  • Page 133 Directory CPU mb2_msg = fr_long( un_regs + MBOX2_A ); if( int_status & LINT_STAT_MBOX3 ) mb3_msg = fr_long( un_regs + MBOX3_A ); /* disable MB ints */ lint_enable = fr_long( un_regs + LINT_EN_A ); lint_enable &= ~(LINT_EN_MBOX3 | LINT_EN_MBOX2 | LINT_EN_MBOX1 | LINT_EN_MBOX0); fw_long( un_regs + LINT_EN_A, lint_enable );...

  • Page 134: File: Cpu.h

    VMIVME-7740 Product Manual ** FILE: CPU.H typedef unsigned char Byte; typedef unsigned short Word; typedef unsigned long Long; /* universe Device ID and Vendor ID */ #define UNIVERSE_VID 0x10E3 #define UNIVERSE_DID 0x0000 /* CPU specific bits located at I/O 0x400 */...

  • Page 135: File: Flat.c

    Directory CPU ** FILE: FLAT.C ** flat.c ** Access flat memory space (up to 4GB) in real mode. #include <stdio.h> #include <dos.h> #include “flat.h” ** Keyboard controller defines #define RAMPORT 0x70 #define KB_PORT 0x64 #define PCNMIPORT 0xA0 #define INBA20 0x60 #define INBA20ON 0xDF #define INBA20OFF 0xDD ** macro to clear keyboard port...
  • Page 136 VMIVME-7740 Product Manual void a20( int flag ) kx(); outp( KB_PORT, 0xD1 ); kx(); outp( INBA20, flag ? INBA20ON : INBA20OFF ); kx(); outp( KB_PORT, 0xFF ); kx(); ** convert a linear address to a far pointer void far * linear_to_seg( FPTR lin ) void far *p;...
  • Page 137 Directory CPU gdtptr.limit = 15; ** disable regular interrupts disable(); ** disable NMI outp( RAMPORT, inp( RAMPORT ) | 0x80 ); ** call protected mode code protinit( &gdtptr ); ** Turn interrupts back on enable(); ** Turn NMI back on outp( RAMPORT, inp( RAMPORT ) &...
  • Page 138 VMIVME-7740 Product Manual mov cr0,eax jmp short nxt nxt: asm { .386P mov bx,8 mov gs,bx mov es,bx and al,0xfe mov cr0,eax int fr_byte( FPTR adr ) int d; asm { .386P xor ax,ax /* zero gs */ mov gs,ax...
  • Page 139 Directory CPU mov gs,ax mov eax, adr mov ax,word ptr gs:[eax] mov d,ax return d; long fr_long( FPTR adr ) long d; asm { .386P xor ax,ax /* zero gs */ mov gs,ax mov eax,adr mov eax,dword ptr gs:[eax] mov d,eax return d;...
  • Page 140 VMIVME-7740 Product Manual asm { .386P xor ax,ax /* zero gs */ mov gs,ax mov eax,a mov bx,d mov word ptr gs:[eax],bx void fw_long( FPTR a, long d ) asm { .386P xor ax,ax /* zero gs */ mov gs,ax...
  • Page 141 Directory CPU mov ecx,n /* This is the number of dwords */ rep movs dword ptr es:[edi],dword ptr gs:[esi] pop es /* give back es */ /* flat move word */ void fmw_string( FPTR d, FPTR s, long n ) asm { .386P /* have to use ES for string move */...
  • Page 142 VMIVME-7740 Product Manual mov ecx,n /* This is the number of bytes */ rep movs byte ptr es:[edi],byte ptr gs:[esi] pop es /* give back es */...

  • Page 143: File: Flat.h

    Directory CPU ** FILE: FLAT.H ** flat.h ** Prototypes typedefs and macros for flat memory access typedef unsigned long FPTR; ** Global descriptor table struct _GDT { unsigned int limit; unsigned int base; unsigned int access; unsigned int hi_limit; static struct _GDT GDT[2]= { {0,0,0,0}, /* Null selector slot */ {0xFFFF,0,0x9200,0x8F}...
  • Page 144 VMIVME-7740 Product Manual ** flat memory function prototypes void a20( int ); void far * linear_to_seg( FPTR ); void extend_seg( void ); void protinit( struct fword * ); int fr_byte( FPTR ); /* flat read byte */ void fw_byte( FPTR, int );...

  • Page 145: File: Pci.c

    Directory CPU ** FILE: PCI.C #include <dos.h> #include <stddef.h> #include “pci.h” #define HIGH_BYTE(ax) (ax >> 8) #define LOW_BYTE(ax) (ax & 0xff) int find_pci_device(unsigned short device_id, unsigned short vendor_id, unsigned short index, unsigned char *bus_number, unsigned char *device_and_function) int ret_status; unsigned short ax, bx, flags; _CX = device_id;...
  • Page 146 VMIVME-7740 Product Manual else ret_status = NOT_SUCCESSFUL; return(ret_status); int read_configuration_area(unsigned char function, unsigned char bus_number, unsigned char device_and_function, unsigned char register_number, unsigned long *data) int ret_status; unsigned short ax, flags; unsigned long ecx; _BH = bus_number; _BL = device_and_function; _DI = register_number;...
  • Page 147 Directory CPU else ret_status = NOT_SUCCESSFUL; return(ret_status); int write_configuration_area(unsigned char function, unsigned char bus_number, unsigned char device_and_function, unsigned char register_number, unsigned long value) int ret_status; unsigned short ax, flags; _BH = bus_number; _BL = device_and_function; _ECX = value; _DI = register_number; _AH = PCI_FUNCTION_ID;...
  • Page 148 VMIVME-7740 Product Manual void outpd(unsigned short port, unsigned long value) _DX = port; _EAX = value; __emit__(0x66, 0xEF); unsigned long inpd(unsigned short port) _DX = port; __emit__(0x66, 0xED); return(_EAX);...

  • Page 149: File: Pci.h

    Directory CPU ** FILE: PCI.H #define TRUE 1 #define FALSE 0 #define CARRY_FLAG 0x01 /* PCI Functions */ #define PCI_FUNCTION_ID 0xB1 #define PCI_BIOS_PRESENT 0x01 #define FIND_PCI_DEVICE 0x02 #define FIND_PCI_CLASS_CODE 0x03 #define READ_CONFIG_BYTE 0x08 #define READ_CONFIG_WORD 0x09 #define READ_CONFIG_DWORD 0x0A #define WRITE_CONFIG_BYTE 0x0B #define WRITE_CONFIG_WORD 0x0C #define WRITE_CONFIG_DWORD 0x0D /* PCI Return codes */...
  • Page 150 VMIVME-7740 Product Manual unsigned char register_number, unsigned long value); void outpd(unsigned short port, unsigned long value); unsigned long inpd(unsigned short port);...

  • Page 151: File: Universe.h

    Directory CPU ** FILE: UNIVERSE.H ** file: universe.h ** header file for the universe II chip register definitions typedef volatile struct universe_regs { unsigned long pci_id; /* PCI device ID vendor ID unsigned long pci_csr; /* PCI config control/status reg unsigned long pci_class;...
  • Page 152 VMIVME-7740 Product Manual unsigned long lsi2_ctl; /* PCI slave image 2 control reg unsigned long lsi2_bs; /* PCI slave image 2 base address reg unsigned long lsi2_bd; /* PCI slave image 2 bound address reg unsigned long lsi2_to; /* PCI slave image 2 translation offset reg */ unsigned long ur2;...
  • Page 153 Directory CPU unsigned long lsi6_bd; /* PCI slave image 6 bound address reg unsigned long lsi6_to; /* PCI slave image 6 translation offset reg */ unsigned long ur7; /* reserved unsigned long lsi7_ctl; /* PCI slave image 7 control reg unsigned long lsi7_bs;...
  • Page 154 VMIVME-7740 Product Manual unsigned long v5_statid; /* VME interrupt status/ID in IRQ5 unsigned long v6_statid; /* VME interrupt status/ID in IRQ6 unsigned long v7_statid; /* VME interrupt status/ID in IRQ7 unsigned long lint_map2; /* PCI interrupt map2 unsigned long vint_map2;...
  • Page 155 Directory CPU unsigned long vsi3_ctl; /* VMEbus slave image 3 control reg unsigned long vsi3_bs; /* VMEbus slave image 3 base address reg unsigned long vsi3_bd; /* VMEbus slave image 3 bound address reg unsigned long vsi3_to; /* VMEbus slave image 3 translation offset */ unsigned long urI[0x06];...
  • Page 156 VMIVME-7740 Product Manual unsigned long vsi7_bd; /* VMEbus slave image 7 bound address reg unsigned long vsi7_to; /* VMEbus slave image 7 translation offset */ unsigned long urP[0x05]; /* reserved unsigned long v_cr_csr; /* VMEbus CR/CSR reserved unsigned long vcsr_clr;...
  • Page 157 Directory CPU #define SCYC_ADDR_A 0x174 /* PCI special cycle PCI address reg #define SCYC_EN_A 0x178 /* PCI special cycle swap/compare enable reg */ #define SCYC_CMP_A 0x17C /* PCI special cycle compare data reg #define SCYC_SWP_A 0x180 /* PCI special cycle swap data reg #define LMISC_A 0x184 /* PCI miscellaneous reg #define SLSI_A...
  • Page 158 VMIVME-7740 Product Manual #define LINT_STAT_A 0x304 /* PCI interrupt status #define LINT_MAP0_A 0x308 /* PCI interrupt map0 #define LINT_MAP1_A 0x30C /* PCI interrupt map1 #define VINT_EN_A 0x310 /* VME interrupt enable #define VINT_STAT_A 0x314 /* VME interrupt status #define VINT_MAP0_A 0x318 /* VME interrupt map0...
  • Page 159 Directory CPU #define VSI1_BS_A 0xF18 /* VMEbus slave image 1 base address reg #define VSI1_BD_A 0xF1C /* VMEbus slave image 1 bound address reg #define VSI1_TO_A 0xF20 /* VMEbus slave image 1 translation offset */ #define VSI2_CTL_A 0xF28 /* VMEbus slave image 2 control reg #define VSI2_BS_A 0xF2C /* VMEbus slave image 2 base address reg #define VSI2_BD_A 0xF30 /* VMEbus slave image 2 bound address reg #define VSI2_TO_A 0xF34 /* VMEbus slave image 2 translation offset */...
  • Page 160 VMIVME-7740 Product Manual #define VSI7_BS_A 0xFD0 /* VMEbus slave image 7 base address reg #define VSI7_BD_A 0xFD4 /* VMEbus slave image 7 bound address reg #define VSI7_TO_A 0xFD8 /* VMEbus slave image 7 translation offset */ #define V_CR_CSR_A 0xFF0 /* VMEbus CR/CSR reserved...
  • Page 161 Directory CPU #define PCI_CSR_S_TA 0x08000000 /* R/WC signalled target abort #define PCI_CSR_DEVSEL 0x02000000 /* R device select timing - medium */ #define PCI_CSR_DP_D 0x01000000 /* RC data parity detected #define PCI_CSR_TFBBC 0x00800000 /* R target fast back-to-back capable */ #define PCI_CSR_MFBBC 0x00000000 /* R master fast back-to-back capable */ #define PCI_CSR_SERR_EN 0x00000100 /* R/W SERR* enable...
  • Page 162 VMIVME-7740 Product Manual #define PCI_MISC1_MAX_LAT 0x00000000 /* R maximum latency: none #define PCI_MISC1_MAX_GNT 0x00030000 /* R minimum grant: 250 ns #define PCI_MISC1_INT_PIN 0x00000100 /* R interrupt pin #define PCI_MISC1_INT_LINE 0x000000FF /* R/W interrupt line MASK /* LSI[X]_ctl - slave image control registers ( lsi0 - lsi7 ) */...
  • Page 163 Directory CPU #define LSI0_BS 0xFFFFF000 /* R/W PCI slave image 0 base address MASK */ #define LSI1_BS 0xFFFF0000 /* R/W PCI slave image 1 base address MASK */ #define LSI2_BS 0xFFFF0000 /* R/W PCI slave image 2 base address MASK */ #define LSI3_BS 0xFFFF0000 /* R/W PCI slave image 3 base address MASK */ #define...
  • Page 164 VMIVME-7740 Product Manual #define SCYC_CTL_RSVD 0x00000003 /* R/W reserved /* scyc_addr - special cycle PCI bus address register 0x0000000X */ #define SCYC_ADDR 0xFFFFFFFC /* R/W spceial cycle PCIbus add reg MASK /* scyc_en - special cycle swap/compare enable reister 0x00000000 */...
  • Page 165 Directory CPU #define SLSI_SUPER 0x00000F00 /* R/W VME supervisor/user AM code MASK #define SLSI_BS 0x000000FC /* R/W base address MASK #define SLSI_LAS_M 0x00000000 /* R/W PCIbus memory space #define SLSI_LAS_IO 0x00000001 /* R/W PCIbus I/O space #define SLSI_LAS_C 0x00000002 /* R/W PCIbus type 1 configuration space */ #define SLSI_LAS_R 0x00000003 /* R/W PCIbus reserved /* l_cmderr - PCI command error log register */...
  • Page 166 VMIVME-7740 Product Manual #define DCTL_VCT_SB 0x00000100 /* R/W VMEbus single cycles and block #define DCTL_LD64EN 0x00000080 /* R/W enable 64 bit PCI transaction /* dtbc - DMA transfer byte count register 0xXX000000 */ #define DTBC 0x00FFFFFF /* R/W DMA xfer byte count MASK...
  • Page 167 Directory CPU #define DGCS_VOFF9 0x00080000 /* R/W min off between xfers 2 us #define DGCS_VOFFA 0x00090000 /* R/W min off between xfers 4 us #define DGCS_VOFFB 0x000A0000 /* R/W min off between xfers 8 us #define DGCS_ACT 0x00008000 /* R DMA active flag #define DGCS_STOP 0x00004000 /* R/WC DMA stopped flag...
  • Page 168 VMIVME-7740 Product Manual #define LINT_EN_VERR 0x00000400 /* R/W PCI VERR interrupt enable #define LINT_EN_LERR 0x00000200 /* R/W PCI LERR interrupt enable #define LINT_EN_DMA 0x00000100 /* R/W PCI DMA interrupt enable #define LINT_EN_VIRQ7 0x00000080 /* R/W VIRQ7 interrupt enable #define LINT_EN_VIRQ6 0x00000040 /* R/W VIRQ6 interrupt enable...
  • Page 169 Directory CPU #define LINT_STAT_VIRQ3 0x00000008 /* R/WC VIRQ3 interrupt received #define LINT_STAT_VIRQ2 0x00000004 /* R/WC VIRQ2 interrupt received #define LINT_STAT_VIRQ1 0x00000002 /* R/WC VIRQ1 interrupt received #define LINT_STAT_VOWN 0x00000001 /* R/WC VOWN interrupt received /* lint_map0 - PCI interrupt map 0 register */ #define LINT_MAP0_VIRQ7_0 0x00000000 /* R/W PCI int LINT#0 for VME IRQ7 #define...
  • Page 170 VMIVME-7740 Product Manual #define LINT_MAP0_VIRQ5_0 0x00000000 /* R/W PCI int LINT#0 for VME IRQ5 #define LINT_MAP0_VIRQ5_1 0x00100000 /* R/W PCI int LINT#1 for VME IRQ5 #define LINT_MAP0_VIRQ5_2 0x00200000 /* R/W PCI int LINT#2 for VME IRQ5 #define LINT_MAP0_VIRQ5_3 0x00300000 /* R/W PCI int LINT#3 for VME IRQ5...
  • Page 171 Directory CPU #define LINT_MAP0_VIRQ3_3 0x00003000 /* R/W PCI int LINT#3 for VME IRQ3 #define LINT_MAP0_VIRQ3_4 0x00004000 /* R/W PCI int LINT#4 for VME IRQ3 #define LINT_MAP0_VIRQ3_5 0x00005000 /* R/W PCI int LINT#5 for VME IRQ3 #define LINT_MAP0_VIRQ3_6 0x00006000 /* R/W PCI int LINT#6 for VME IRQ3 #define LINT_MAP0_VIRQ3_7 0x00007000 /* R/W PCI int LINT#7 for VME IRQ3 #define...
  • Page 172 VMIVME-7740 Product Manual #define LINT_MAP0_VIRQ1_6 0x00000060 /* R/W PCI int LINT#6 for VME IRQ1 #define LINT_MAP0_VIRQ1_7 0x00000070 /* R/W PCI int LINT#7 for VME IRQ1 #define LINT_MAP0_VOWN_0 0x00000000 /* R/W PCI int LINT#0 for VME OWN */ #define LINT_MAP0_VOWN_1 0x00000001 /* R/W PCI int LINT#1 for VME...
  • Page 173 Directory CPU #define LINT_MAP1_SYSFAIL_0 0x00000000 /* R/W PCI int LINT#0 for SYSFAIL #define LINT_MAP1_SYSFAIL_1 0x01000000 /* R/W PCI int LINT#1 for SYSFAIL #define LINT_MAP1_SYSFAIL_2 0x02000000 /* R/W PCI int LINT#2 for SYSFAIL #define LINT_MAP1_SYSFAIL_3 0x03000000 /* R/W PCI int LINT#3 for SYSFAIL #define LINT_MAP1_SYSFAIL_4 0x04000000 /* R/W PCI int LINT#4 for SYSFAIL #define...
  • Page 174 VMIVME-7740 Product Manual #define LINT_MAP1_SW_IACK_3 0x00030000 /* R/W PCI int LINT#3 for SW_IACK */ #define LINT_MAP1_SW_IACK_4 0x00040000 /* R/W PCI int LINT#4 for SW_IACK */ #define LINT_MAP1_SW_IACK_5 0x00050000 /* R/W PCI int LINT#5 for SW_IACK */ #define LINT_MAP1_SW_IACK_6 0x00060000 /* R/W PCI int LINT#6 for...
  • Page 175 Directory CPU /* vint_en - VMEbus interrupt enable register */ #define VINT_EN_SW7 0x80000000 /* R/W enable VMEbus int SW7 #define VINT_EN_SW6 0x40000000 /* R/W enable VMEbus int SW6 #define VINT_EN_SW5 0x20000000 /* R/W enable VMEbus int SW5 #define VINT_EN_SW4 0x10000000 /* R/W enable VMEbus int SW4 #define VINT_EN_SW3 0x08000000 /* R/W enable VMEbus int SW3...
  • Page 176 VMIVME-7740 Product Manual #define VINT_STAT_SW3 0x08000000 /* R/W VMEbus int SW3 #define VINT_STAT_SW2 0x04000000 /* R/W VMEbus int SW2 #define VINT_STAT_SW1 0x02000000 /* R/W VMEbus int SW1 #define VINT_STAT_MBOX3 0x00080000 /* R/W VMEbus int MAILBOX 3 #define VINT_STAT_MBOX2 0x00040000 /* R/W VMEbus int MAILBOX 2...
  • Page 177 Directory CPU #define VINT_MAP0_LINT6_2 0x02000000 /* R/W VME int 2 for LINT6 #define VINT_MAP0_LINT6_3 0x03000000 /* R/W VME int 3 for LINT6 #define VINT_MAP0_LINT6_4 0x04000000 /* R/W VME int 4 for LINT6 #define VINT_MAP0_LINT6_5 0x05000000 /* R/W VME int 5 for LINT6 #define VINT_MAP0_LINT6_6 0x06000000 /* R/W VME int 6 for LINT6 #define...
  • Page 178 VMIVME-7740 Product Manual #define VINT_MAP0_LINT2_D 0x00000000 /* R/W VME int disable for LINT2 #define VINT_MAP0_LINT2_1 0x00000100 /* R/W VME int 1 for LINT2 #define VINT_MAP0_LINT2_2 0x00000200 /* R/W VME int 2 for LINT2 #define VINT_MAP0_LINT2_3 0x00000300 /* R/W VME int 3 for LINT2...
  • Page 179 Directory CPU #define VINT_MAP1_SW_IACK_3 0x00030000 /* R/W VME int 3 for SW_IACK #define VINT_MAP1_SW_IACK_4 0x00040000 /* R/W VME int 4 for SW_IACK #define VINT_MAP1_SW_IACK_5 0x00050000 /* R/W VME int 5 for SW_IACK #define VINT_MAP1_SW_IACK_6 0x00060000 /* R/W VME int 6 for SW_IACK #define VINT_MAP1_SW_IACK_7 0x00070000 /* R/W VME int 7 for SW_IACK #define...
  • Page 180 VMIVME-7740 Product Manual #define VINT_MAP1_DMA_6 0x00000006 /* R/W VME int 6 for DMA #define VINT_MAP1_DMA_7 0x00000007 /* R/W VME int 7 for DMA /* statid - interrupt STATUS/ID OUT 0x00XXXXXX */ #define STATID 0xFF000000 /* R/W interrupt status/ID out MASK */...
  • Page 181 Directory CPU #define LINT_MAP2_LM2_3 0x03000000 /* R/W PCI int LINT#3 for LOC MON2 #define LINT_MAP2_LM2_4 0x04000000 /* R/W PCI int LINT#4 for LOC MON2 #define LINT_MAP2_LM2_5 0x05000000 /* R/W PCI int LINT#5 for LOC MON2 #define LINT_MAP2_LM2_6 0x06000000 /* R/W PCI int LINT#6 for LOC MON2 #define LINT_MAP2_LM2_7 0x07000000 /* R/W PCI int LINT#7 for LOC MON2...
  • Page 182 VMIVME-7740 Product Manual #define LINT_MAP2_LM0_6 0x00060000 /* R/W PCI int LINT#6 for LOC_MON0 */ #define LINT_MAP2_LM0_7 0x00070000 /* R/W PCI int LINT#7 for LOC_MON0 */ #define LINT_MAP2_MB3_0 0x00000000 /* R/W PCI int LINT#0 for MAILBOX3 #define LINT_MAP2_MB3_1 0x00001000 /* R/W PCI int LINT#1 for MAILBOX3...
  • Page 183 Directory CPU #define LINT_MAP2_MB1_1 0x00000010 /* R/W PCI int LINT#1 for MAILBOX1 #define LINT_MAP2_MB1_2 0x00000020 /* R/W PCI int LINT#2 for MAILBOX1 #define LINT_MAP2_MB1_3 0x00000030 /* R/W PCI int LINT#3 for MAILBOX1 #define LINT_MAP2_MB1_4 0x00000040 /* R/W PCI int LINT#4 for MAILBOX1 #define LINT_MAP2_MB1_5 0x00000050 /* R/W PCI int LINT#5 for MAILBOX1...
  • Page 184 VMIVME-7740 Product Manual #define VINT_MAP2_MB3_4 0x00004000 /* R/W VME int VIRQ#4 for MAILBOX3 */ #define VINT_MAP2_MB3_5 0x00005000 /* R/W VME int VIRQ#5 for MAILBOX3 */ #define VINT_MAP2_MB3_6 0x00006000 /* R/W VME int VIRQ#6 for MAILBOX3 */ #define VINT_MAP2_MB3_7 0x00007000 /* R/W VME int VIRQ#7 for...
  • Page 185 Directory CPU #define VINT_MAP2_MB0_2 0x00000002 /* R/W VME int VIRQ#2 for MAILBOX0 */ #define VINT_MAP2_MB0_3 0x00000003 /* R/W VME int VIRQ#3 for MAILBOX0 */ #define VINT_MAP2_MB0_4 0x00000004 /* R/W VME int VIRQ#4 for MAILBOX0 */ #define VINT_MAP2_MB0_5 0x00000005 /* R/W VME int VIRQ#5 for MAILBOX0 */ #define VINT_MAP2_MB0_6...
  • Page 186 VMIVME-7740 Product Manual #define MAST_CTL_VRL_0 0x00000000 /* R/W VMEbus request level 0 #define MAST_CTL_VRL_1 0x00400000 /* R/W VMEbus request level 1 #define MAST_CTL_VRL_2 0x00800000 /* R/W VMEbus request level 2 #define MAST_CTL_VRL_3 0x00C00000 /* R/W VMEbus request level 3 #define...
  • Page 187 Directory CPU #define MISC_CTL_VARBTO_2 0x01000000 /* R/W VME arb. time out 16 us #define MISC_CTL_VARBTO_3 0x02000000 /* R/W VME arb. time out 256 us #define MISC_CTL_SW_LRST 0x00800000 /* W software PCI reset #define MISC_CTL_SW_SRST 0x00400000 /* W software VME sysrest #define MISC_CTL_BI 0x00100000 /* R/W universe in BI-Mode...
  • Page 188 VMIVME-7740 Product Manual #define VSI_CTL_VAS_16 0x00000000 /* R/W address space A16 #define VSI_CTL_VAS_24 0x00010000 /* R/W address space A24 #define VSI_CTL_VAS_32 0x00020000 /* R/W address space A32 #define VSI_CTL_VAS_R1 0x00030000 /* R/W address space reserved 1 #define VSI_CTL_VAS_R2 0x00040000 /* R/W address space reserved 2...
  • Page 189 Directory CPU #define LM_CTL_AM_D 0x00400000 /* R/W location monitor AM = DATA #define LM_CTL_AM_P 0x00800000 /* R/W location monitor AM = PROGRAM #define LM_CTL_AM_DP 0x00C00000 /* R/W location monitor AM = BOTH #define LM_CTL_AM_U 0x00100000 /* R/W location monitor AM = USER #define LM_CTL_AM_S 0x00200000 /* R/W location monitor AM = SUPER */...
  • Page 190 VMIVME-7740 Product Manual #define V_AMERR_IACK 0x02000000 /* R VMEbus IACK #define V_AMERR_M_ERR 0x01000000 /* R multiple errors occurred #define V_AMERR_V_STAT 0x00800000 /* R/W VME error logs are valid /* vaerr - VMEbus address error log */ #define VAERR 0xFFFFFFFF /* R VMEbus address error log MASK */...

  • Page 191: Directory Sram

    Directory SRAM Directory SRAM The file in this directory can be used to test the integrity of the battery backed SRAM. ** FILE: TS.C /****************************************************************************/ /* FILE: TS.C /* Test battery backed SRAM with patterns and data=address. /****************************************************************************/ #include <stdlib.h> #include <stdio.h>...
  • Page 192 VMIVME-7740 Product Manual unsigned long lrd; printf(“\nTesting 32K SRAM DATA/~DATA B/W/L/ADDR .....”); buf_ptr = (unsigned int far *) MK_FP( 0xD800, 0x18 ); /* fill and test buf with DATA/~DATA BYTES 4 patterns */ for( x = 0; x < 4; x++ ) { b_ptr = (unsigned char far *) buf_ptr;...
  • Page 193 Directory SRAM wdat = (unsigned int) pat[x]; for( i = 0x18; i < 0x8000; i+=2 ) { wrd = *w_ptr++; if( wdat != wrd ) { printf(“FAILED\nWORD DATA @ ADDR: %Fp WR: %.4X RD: %.4X\n”, --w_ptr, wdat, wrd ); exit( 1 ); wdat = ~wdat;...
  • Page 194 VMIVME-7740 Product Manual for( x = 0; x < 4; x++ ) { l_ptr = (unsigned long far *) MK_FP( 0xD800, 0x18 ); for( i = 0x18; i < 0x8000; i+=4 ) { *l_ptr++ = i; l_ptr = (unsigned long far *) MK_FP( 0xD800, 0x18 );...

  • Page 195: Directory Timers

    This directory contains sample code useful in the creation of applications involving the VMIVME-7740’s three software controlled 16-bit timers. The code is written for the control of a single timer, but can be utilized in generating code for any timer configuration.
  • Page 196 VMIVME-7740 Product Manual #define CW_CLC 0x00 /* W Cntr latch command (cnt/stat) #define CW_SLC 0x00 /* W Status latch command #define CW_LSB 0x10 /* W LSB only #define CW_MSB 0x20 /* W MSB only #define CW_LSBMSB 0x30 /* W LSB first then MSB...

  • Page 197: File: T_Timers.c

    Directory Timers ** FILE: T_TIMERS.C /****************************************************************************/ /* FILE: T_TIMER.C /****************************************************************************/ #include <stdlib.h> #include <stdio.h> #include <string.h> #include <conio.h> #include <ctype.h> #include <dos.h> #include “pci.h” #include “cpu.h” /* T_TIMER.C function prototypes */ void do_exit( int ); /* TIMERS.C function prototypes */ void far interrupt irq_rcvd( void );...
  • Page 198 VMIVME-7740 Product Manual unsigned int timer_base; unsigned char pic1_org; unsigned char gpo_org; void main( int argc, char * argv[]) unsigned long t1, t2, t3; int test_int; unsigned long temp_dword; char user[80]; timer_base = 0x500; /* try to locate the power management device on the PCI bus */ test_int = find_pci_device(DID_PWR_MGM, VID_PWR_MGM, 0, &bus, &dev_func);...
  • Page 199 Directory Timers pic1_org = inp(0x21) & 0xFF; /* slave mask bits */ /* disable interrupt 5 */ outp(0x21, (pic1_org | 0x20) ); /* 0 = enable 1 = disable */ enable(); gpo_org = inp( gpo_base ) & 0xFF; /* setup timers interrupt service routine */ init_timer_int();...
  • Page 200 VMIVME-7740 Product Manual outp( timer_base + TIMER_CNTL, (CW_SC0 | CW_LSBMSB | CW_M2) ); tmr_status = 0; test_int = 100; load_counter( 2, 0xFFFF ); if( t2_count ) { t2++; break; test_int--; delay( 1 ); } while( test_int ); /* disable timers by reloading the control word */ outp( timer_base + TIMER_CNTL, (CW_SC1 | CW_LSBMSB | CW_M2) );...
  • Page 201 Directory Timers outp( gpo_base, ( gpo_org | GPO_T1 | GPO_T2 | GPO_T3 ) ); if( t1 && t2 && t3 ) printf(“PASSED\n”); else printf(“FAILED\n”); if( !t1 ) printf(“TIMER 1 failed\n”); if( !t2 ) printf(“TIMER 2 failed\n”); if( !t3 ) printf(“TIMER 3 failed\n”); do_exit( 2 );...
  • Page 202 VMIVME-7740 Product Manual #include <conio.h> #include “cpu.h” /* function prototypes */ void far interrupt irq_rcvd( void ); void init_timer_int( void ); void restore_orig_int( void ); void load_counter( int, unsigned int ); void read_counter( int, unsigned int *, unsigned char * );...
  • Page 203 Directory Timers /* return value: none /*******************************************************************/ void init_timer_int( void ) disable(); old_vect = getvect( IRQ5 ); /* save vector for IRQ5 */ setvect( IRQ5, irq_rcvd ); /* enable interrupt 5 */ outp(0x21, (pic1_org & 0xDF) ); /* 0 = enable 1 = disable */ /* clear all three GPO inputs */ outp( gpo_base, ( gpo_org &...
  • Page 204 VMIVME-7740 Product Manual disable(); outp(0x21, pic1_org); setvect( IRQ5, old_vect ); enable(); } /* restore_orig_int */ /*******************************************************************/ /* load_counter() /* purpose: Loads the appropriate counter with the count passed */ /*******************************************************************/ /* parameters: int counter = 1, 2, 3 for COUNTER 1, 2, or 3...
  • Page 205 Directory Timers outp( timer_base + TIMER_CNTR2, (unsigned char) msb ); break; case 3: /* select counter 3, LSB then MSB, mode 2 */ outp( timer_base + TIMER_CNTL, (CW_SC2 | CW_LSBMSB | CW_M2) ); outp( timer_base + TIMER_CNTR3, (unsigned char) lsb ); outp( timer_base + TIMER_CNTR3, (unsigned char) msb );...
  • Page 206 VMIVME-7740 Product Manual *status = inp( timer_base + TIMER_CNTR1 ) & 0xFF; lsb = inp( timer_base + TIMER_CNTR1 ) & 0xFF; msb = inp( timer_base + TIMER_CNTR1 ) & 0xFF; msb = msb << 8; *count = ( lsb | msb );...
  • Page 207 Directory Timers /*******************************************************************/ /* parameters: none /*******************************************************************/ /* return value: none /*******************************************************************/ void interrupt irq_rcvd(void) disable(); asm { .386P push eax push ebx tmr_status = inp( gpi_base ) & 0xFF; /* increment counts and clear status */ if( tmr_status & GPI_T1 ) { t1_count++;...
  • Page 208 VMIVME-7740 Product Manual pop ebx pop eax enable();...

  • Page 209: Directory Watchdog

    Directory WATCHDOG Directory WATCHDOG This directory contains sample code useful in the creation of applications involving the VMIVME-7740’s Watchdog Timer function as described in Chapter 4. ** FILE: WATCHDOG.H ** DS1384 REGISTER OFFSETS /* 7 6 5 4 3 2 1 0 */...

  • Page 210: File:wdto.c

    VMIVME-7740 Product Manual ** FILE:WDTO.C /****************************************************************************/ /* FILE: WDTO_RST.C /* Setup watchdog to issue reset on time out. /****************************************************************************/ #include <stdlib.h> #include <stdio.h> #include <dos.h> #include <time.h> #include <conio.h> #include <ctype.h> #include “watchdog.h” unsigned char far * wd_ptr; time_t t;...
  • Page 211 Directory WATCHDOG time(&t); printf(“START DATE & TIME: %.24s\n\n”, ctime(&t) ); do { time(&t); printf(“CURRENT DATE & TIME: %.24s\r”, ctime(&t) ); delay( 250 ); } while( !kbhit() ); } /* end main */...
  • Page 212 VMIVME-7740 Product Manual...
  • Page 213 Index Numerics 100BaseTx Floppy Disk Drive 51, 79 10BaseT Floppy Drive A 82C54 Floppy Drive B floppy mapping functional diagram address map AGP controller auxiliary I/O mapping graphics video resolutions 36, 48, 114 BIOS Halt On BIOS setup screens hexadecimal block diagram 42, 118 CMOS configuration...
  • Page 214 VMIVME-7740 Product Manual keyboard connector screen resolutions Select Timer Serial I/O (COM1,2,3 & 4) serial port connector, D9 or RJ45 serial port mapping LPT1 Parallel I/O serial ports LPT2 Parallel I/O SERR interrupt Setting The Time SIZE SMC Super-I/O chip...

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