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DPS-V55/V55M
• Waveforms
– MAIN BOARD –
1 IC501 3 (MCLK) , IC5513 (MCLK)
6 IC502 @¡ (BCKO)
3.8 Vp-p
12.288 MHz
2 IC501 4 (LRCK), IC551 4 (LRCK)
7 IC504 2 (OUT)
5.4 Vp-p
48 kHz
3 IC501 5 (SCLK), IC551 5 (SCLK)
8 IC506 2 (CLK), IC507 2 (CLK)
5.3 Vp-p
3.072 MHz
4 IC502 !£ (CLK0)
9 IC506 !£ (QB)
3.2 Vp-p
49.152 MHz
5 IC502 !ª (LRKO)
0 IC507 !¡ (QD)
5.3 Vp-p
48 kHz
!¡ IC701 *™ (X0)
5.3 Vp-p
3.072 MHz
4 MHz
4.6 Vp-p
49.152 MHz
2.8 Vp-p
12.288 MHz
6.3 Vp-p
3.072 MHz
6.2 Vp-p
48 kHz
– 27 –
5-7. IC PIN FUNCTION DESCRIPTION
• MAIN BOARD IC502 CXD2707Q (DSP)
Pin No.
Pin Name
I/O
1
EA9
O
Address signal output to the external RAM device Not used (open)
2
EC0
O
Address signal output to the memory (IC503)
4.9 Vp-p
3
VDD
—
Power supply terminal (+5V)
4
VSS
—
Ground terminal
5, 6
EC1, EC2
O
Address signal output to the external RAM device Not used (open)
7 to 9
EA13 to EA15
O
Address signal output to the external RAM device Not used (open)
10
TST
I
Input terminal for the test Not used (fixed at "L")
11
TDR
I
Input terminal for the test Not used (fixed at "L")
12
BFOT
O
Master clock buffer output terminal Not used (open)
13
CLKO
O
Master clock output terminal (49.152 MHz)
14
CLKI
I
Master clock input terminal (49.152 MHz)
15
VSS
—
Ground terminal
16
TS0
I
Input terminal for the test Not used (fixed at "L")
17
TS1
I
Input terminal for the test Not used (fixed at "L")
18
TSA
I
Input terminal for the test Not used (fixed at "L")
19
LRK0
I
L/R sampling clock signal input of the serial in/out data
20
LRK1
I
L/R sampling clock signal input of the serial in/out data Not used (fixed at "L")
21
BCK0
I
Bit clock signal input of the serial in/out data
22
BCK1
I
Bit clock signal input of the serial in/out data Not used (fixed at "L")
23
BCT
O
Divider output for the bit clock signal Not used (open)
24
LCT
I/O
Counter input for the cycle detect/divider LRCK output terminal Not used (open)
25
SIA
I
Serial data (for sound) input from the CS4222 (IC501)
26
SIB
I
Serial data (for sound) input from the CS4222 (IC551)
27
SIC
I
Serial data (for sound) input terminal Not used (fixed at "L")
28
VDD
—
Power supply terminal (+5V)
29
VSS
—
Ground terminal
30
SOA
O
Serial data (for sound) output to the CS4222 (IC501)
31
SOB
O
Serial data (for sound) output to the CS4222 (IC551)
32
SOC
O
Serial data (for sound) output terminal Not used (open)
33
ECJ0
I/O
Input for the jump condition/test data output terminal Not used (fixed at "L")
34
ECJ1
I/O
Input for the jump condition/test data output terminal Not used (fixed at "L")
35
ECJ2
I/O
Input for the jump condition/test data output terminal Not used (fixed at "L")
36
ECJ3
I/O
Input for the jump condition/test data output terminal Not used (fixed at "L")
37
REDY
O
Ready signal output to the CPU (IC701) "L": busy status
38
TRDT
O
Communication serial data output to the CPU (IC701)
39
XLAT
I
Serial data latch pulse input from the CPU (IC701)
40
VSS
—
Ground terminal
41
SCK
I
Communication serial data transfer clock signal input from the CPU (IC701)
42
RVDT
I
Communication serial data input from the CPU (IC701)
43
SCL0
O
Output terminal for the test Not used (open)
44
SCL1
O
Output terminal for the test Not used (open)
45
LR0F
O
Output terminal for the test Not used (open)
46
LR1F
O
Output terminal for the test Not used (open)
47
XRST
I
System reset signal input from the reset signal generator (IC703) "L": reset
48
ED0
I/O
Two-way data bus with the external RAM device Not used
Function
– 28 –
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