Ic Pin Function - Sony Walkman PCM-M1 Service Manual

4-7.

IC PIN FUNCTION

• IC506 CXD2607BR
Pin No. Pin Name I/O
1 Vpp O
2 A10 O
3 A11 —
4 A12 O
5 A13 O
6 A14 O
7 XWE O
8 WOE O
9 XEAN O
10 TST1
11 XT10 O
12 XT11
13 Vss —
14 XRST
15 CLKO O
16 MINT O
17 ATSY
18 MCLK O
19 DREF O
20 SBPM O
21 EXCK
22 SDSI
23 SDSO O
24 SBSY O
25 RFPL O
26 CCLK O
27 MUTE O
28 MUTM O
29 UNLK O
30 RFCT
31 SYMN O
32 SELB
33 PLCK O
34 TST2
35 RFDT
36 XCS
37 SWP
38 Vss —
39 PIPC O
40 REPB O
41 REDT O
42 TST4
43 PDO O
44 SELC
45 MUTA
46 PLCO
47 PLVR O
48 PLRF O
49 MSSL
50 RX
+5v
External RAM address input.
External RAM address input.
External RAM address input.
External RAM address input.
External RAM address input.
External RAM write enable signal output.
External RAM output enable signal output.
External addressing enable signal output.
I Test input, fixed to "L".
X'tal oscillator circuit -1 output (not used).
I X'tal oscillator circuit -1 input (not used).
GND.
I Reset input. Reset at "L".
System clock output (Frequency is 4.9152 MHz when SELC = "L", 8.192 MHz when SELC = "H").
* 1 control byte (1). Q code decode (music interval detection) output when bit 1 = "L", BCK clock output from
RX-PLL when bit 1 = "H").
I ATF sync signal input.
Channel clock (fch) output.
Signal output with duty 50 at SBSY rate.
Control byte (1). Data transfer monitoring signal output with microprocessor when bit 1 = "L" (Transfer is
enabled at "L"), f256 clock output from RX-PLL when bit 1 = "H").
I Clock input for data transfer with microprocessor.
I Serial data input from microprocessor.
Serial data output to microprocessor.
Frame cycle signal output for data transfer with microprocessor.
PLL clock divided-by-5880 output.
9.8304 MHz output when SELC = "L", 12.288 MHz output when SELC = "H".
Mute input, mute at "H". REC monitor sound is not muted.
Mute monitor. The mute status is indicated by "H".
RXPLL lock monitor signal output. Indicates the RXPLL is locked.
I Playback RF signal control (RF signal is valid at "L", RF signal is invalid at "H".)
Monitor signal indicating result of CI check which supports RF.
I Oscillating frequency selection signal input.
Control byte (1). RFPLL clock output when bit 1 = "L", f128 clock output from RX-PLL when bit 1 = "H").
I Test terminal, fixed to "L".
I Playback RF signal input.
I Chip select input for data transfer with microprocessor. Transfer enable at "L".
I RF switching pulse. "A" track at "L". "B" track at "H".
GND.
ATF pilot signal of wiring signal/identification signal output. Pilot signal at "H".
REC/PB discriminating signal input. REC state at "H".
Wiring signal output.
I Test terminal, fixed to "L".
Phase comparator output for RXPLL.
I Oscillating frequency selection signal input.
I Mute input, mute at "H". REC monitor sound is also muted.
I External VCO clock input of RXPLL. (512 fs reference).
Phase comparator signal output for RXPLL. (2 fs generated from PLL clock).
Phase comparator signal output for RXPLL. (2 fs of rxx sync detection signal).
I Master mode/slave mode select. Master at "H".
I Digital interface signal input.
Description
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