Specifications - Intel iSBC 80/30 Manual

inter
iSBC® 80/30 SINGLE BOARD COMPUTER
a byte of information is ready to be transferred to the
CPU (Le., input buffer is full) or a byte of information
has been transferred to a peripheral device (Le., out-
put buffer is empty). Two jumper selectable interrupt
requests can be automatically generated by the
USART when a character is ready to be transferred
to the CPU (Le., receive channel buffer is full), or a
Table 3. Programmable Interrupt Modes
Mode Operation
Fully Interrupt request line priorities
Nested
fixed at 0 as highest, 7 as
lowest.
Auto- Equal priority. Each level, after
rotating
receiving service, becomes the
lowest priority level until next
interrupt occurs.
Specific System software assigns lowest
Priority
priority level. Priority of all other
levels based in sequence
numerically on this assignment.
Polled System software examines
priority-encoded system
interrupt status via interrupt
status register.
character is ready to be transmitted (Le., transmit
channel data buffer is empty). A jumper selectable
request can be generated by each of the program-
mable timers and by the universal peripheral inter-
face, eight additional interrupt request lines are
available to the user for direct interface to user des-
ignated peripheral devices via the system bus, and
two interrupt request lines may be jumper routed di-
rectly from peripherals via the parallel I/O driver/ter-
minator section. "
Power-Fail Control
Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal from
the iSBC 635 Power Supply or equivalent.
Expansion Capabilities
Memory and I/O capacity may be expanded and ad-
ditionaJ functions added by using Intel MULTIBUS
compatible expansion boards. High speed integer
and floating point arithmetic capabilities may be add-
ed by using the iSBC 31 OA High Speed Mathematics
Unit. Memory may be expanded to 65,536 bytes by
adding user specified combinations of RAM boards,
EPROM boards, or combination boards. Input/out-
put capacity may be increased by adding digital I/O
and analog I/O expansion boards. Mass storage ca-
pability may be achieved by adding single or double
3-31
density diskette controllers as sub-systems. Modular
expandable backplanes "and cardcages are available
to support multi-board systems.
SPECIFICATIONS
Word Size
Instruction: 8, 16, or 24 bits
Data: 8 bits
Cycle Time
Basic Instruction Cycle: 1.45 J-Ls
NOTE:
Basic instruction cycle is defined as the fastest in-
struction (Le., four clock cycles).
Memory Addressing
On-Board ROM/EPROM: 0-07FF (using 2708 or
2758 EPROMs); O-OFFF (using 2716 EPROMs); 0-
1 FFF (using 2716 EPROMs; 0-1 FFF (using 2732
EPROMs).
On-Board RAM: 16K bytes of dual port RAM starting
on a 16K boundary. One or two 8 K-byte segments
may be reserved for CPU use only.
Memory Capacity
On-Board Read Only Memory: 8K bytes (sockets
only)
On-Board RAM: 16K bytes
Off-Board Expansion: Up to 65,536 bytes in user
specified combinations of RAM, ROM, and EPROM
NOTE:
Read only memory may be added in 1 K, 2K, or 4K
byte increments.
I/O Addressing
On-Board Programmable: I/O (see Table 1)
Port
8255A 8041A18741A USART
1 1 21 3 IControl
Data
I
Control OatalControl
Address EsIE91EAI EB E4 or EsIE5 or E7 EC 1 ED