Pioneer DEH-P90HDD Service Manual page 132

DEH-P90HDD,P900HDD
Pin No. Pin Name
69 BSI0
70 BSO0
71 AVDD
72 AVSS
73 TEMP
74 ATAVSENS
75 KD5
76-80 KD4-0
81 VDD
82 VSS
83 MUTE
84 CDINTB
85 ATARST
86 CDRSTB
87 CDPW
88 CDCE
89 ATAPW
90 BMUTE
91 WAIT
92 BCYST
93 CTS
94 RTS
95 RD
96 UWR
97 LWR
98 VDD
99 VSS
100 MSLOCKIN
101 MODELIN0
102 IORD
103 CS4(ATA)
104 CS3(CXD1859)
105 IOWR
106 DALMON
107 CS0(SRAM)
108 UBE
109 LBE
110 FLWRCNT
111 XPW
112 VDD
113 VSS
114-115 A25-24
116 ADCRST
117 XLED
118 XRST
119-123 A20-16
124 VDD
125 VSS
126-133 A15-8
134 VDD
135 VSS
136-142 A7-1
143 SUBOK
144 D15
132
I/O Function and Operation
I System: input of P-BUS data
O System: output of P-BUS data
AVDD
AVSS
I Input of temperature sensing
I Input of sensing VD power supply voltage in the ATA section
I Input of status of DSP initialization
Input from analog keys 5 - 0 → 4 - 0
I
VDD
VSS
O Output of final muting of the analog system
I LC78683E: input of interrupt request signals
O ATA: output of device reset signals
O LC78683E: output of reset
O Output of controls of power supply to CD-ROM/MP3 section
O LC78683E: output of chip enable
O Output of controls of power supply to the ATA section
O Output of muting for the digital DSP
O
H2: output sampling rate of signals output from CD mechanism to
the DSP microcomputer
O
H2: output sampling rate of signals output from CD mechanism to
the DSP microcomputer
I FL display: input of CTS
O Output of operation-demanding triggers to the DSP
microcomputer/DAC
O Output of read strobe signals
O Output of write-enable signals for upper bytes
O Output of write-enable signals for lower bytes
VDD
VSS
I Input of detection of MS half lock (fully inserted)
I Input of settings of models
O ATA: read strobe for DMA flyby transfer
O Chip selection (ATA section)
O Chip selection (CXD859 section)
O ATA: write strobe for DMA flyby transfer
O Output of settings of power saving
O SRAM chip selection
O Output of enable signals for upper bytes
O Output of enable signals for lower bytes
O
Output of controls of power supply for Flash EP-ROM self-rewriting
O Output of controls of power supply to CXD1859 section
VDD
VSS
O Output of address bus (bit18 - bit0)
O Output of controls of resetting the external A/D
O MS access indicator
O CXD1859: output of reset
O Output of address bus (bit18 - bit0)
VDD
VSS
O Output of address bus (bit18 - bit0)
VDD
VSS
O Output of address bus (bit18 - bit0)
I H2: input from SUBOK pin of CD mechanism's P-BUS
I/O Input /output of data bus (bit15 - bit0)