Ordering Information - Harman Kardon HK 990/230 Service Manual

DESCRIPTION
The Hynix HY57V641620E(L/S)T(P) series is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory
applications which require wide data I/O and high bandwidth. HY57V641620E(L/S)T(P) is organized as 4banks of
1,048,576x16.
HY57V641620E(L/S)T(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs
and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve
very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
• Voltage: VDD, VDDQ 3.3V supply voltage
• All device pins are compatible with LVTTL interface
• 54 Pin TSOPII (Lead or Lead Free Package)
• All inputs and outputs referenced to positive edge of
system clock
• Data mask function by UDQM, LDQM
• Internal four banks operation

ORDERING INFORMATION

Part No.
HY57V641620E(L/S)T(P)-5I
HY57V641620E(L/S)T(P)-6I
HY57V641620E(L/S)T(P)-7I
HY57V641620E(L/S)T(P)-HI
Note: 1. HY57V641620ET-xI Series: Normal power, Leaded.
2. HY57V641620ELT-xI Series: Low power, Leaded.
3. HY57V641620EST-xI Series: Super Low power, Leaded.
4. HY57V641620ETP-xI Series: Normal power, Lead Free.
5. HY57V641620ELTP-xI Series: Low power, Lead Free.
6. HY57V641620ESTP-xI Series: Super Low Power, Lead Free
Rev. 1.5 / Feb. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit)
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Clock Frequency Organization
200MHz
166MHz
4Banks x 1Mbits x16
143MHz
133MHz
32
HY57V641620E(L/S)T(P)-xI Series
Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency; 2, 3 Clocks
Burst Read Single Write operation
Interface
LVTTL
Package
54 Pin TSOPII