Ic Data - Yamaha MX-D1 Service Manual

I IC DATA
IC107: YDA133-E (MAIN P.C.B)
Digital Audio Power Amplifier Controller
PLLC
SEL
AX1
AINM
AINP
VDD
GND
VSS
DETA2
DETB2
DETA
DETB
No. Name I/O
1 GND
2 PLLC AO
3 SEL I
4 AX1 AO
5 AINM AI
6 AINP AI
7 VDD
8 VSS
9 ERRIN I
10 ICOUT OD
11 DETA AI
12 DETA2 AI
13 DETB AIO
14 DETB2 AI
15 MUTEN I
16 PVDD
17 PVSS
18 HIN O
19 HIP O
20 MSSEL I
21 CKOUT O
22 MCKIO IO
23 XI I
24 XO O
Note)
AO : Analog Output
AI : Analog Input
AIO : Analog Input/Output
OD : Open Drain Output
PVDD and VDD are shortcircuited on the board.
PVSS and VSS are shortcircuited on the board.
GND is grounded on the board.
1)
* CERALOCK of subsequent explanation is the registered trademark of Murata Manufacturing Co., Ltd.
2
PLL
3
4
5
Digital
–
modulation
+
6
circuit
Operational
7
amplifier
for integration
1
Digital modulation part
8
12
Power supply
14
voltage
detection
11
circuit
13
Function
Ground
Connecting Loop Filter for Internal PLL
Test
Precision Input Stage Operational Amplifier Output
Precision Input Stage Operational Amplifier Inversion Input
Precision Input Stage Operational Amplifier Non-inversion Input
Input Stage Analog Circuit Positive Power Supply
Input Stage Analog Circuit Negative Power Supply
Error Recognition Signal Input
Error Recognition Signal Output
Setting Reference Voltage for VPP and VMM Voltage Detection
Setting Open Loop Gain of Digital Amplifier
Connecting Capacitor for Setting Power Supply Tuning on Wait Time
Setting Digital Amplifier Open Loop Gain
Setting Mute
Positive Power Supply for Output Buffer
Negative Power Supply for Output Buffer
Digital Modulation Signal Inversion Output
Digital Modulation Signal Non-inversion Output
Changing Mode between Master and Slave
Local Power Supply Driving Clock Output
Clock Input/Output
1)
5.6 MHz CERALOCK * Connection Input
1)
5.6 MHz CERALOCK * Connection Output
24 XO
23 XI
Clock
part
22 MCKIO
20 MSSEL
21 CKOUT
19 HIP
18 HIN
16 PVDD
17 PVSS
15 MUTEN
MUTE
ERROR
9 ERRIN
Control
circuit
10 ICOUT
GND
MX-D1
(Unconnected)
19