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Clock for URSA9
LM14_URSA9_crystalcap
XIN_URSA
XO_URSA
SPI Flash
MX25L3206EM2I-12G
CS#
SPI_CZ_URSA9
SO/SIO1
R1904
33
SPI_DO_URSA9
WP#
R1905
1K
FLASH_WP_URSA
U_SPI_WP_f_URSA
GND
R1932
1K
FRC_FLASH_WP
U_SPI_WP_f_SoC
Chip Config
Debug/ISP ADDR
Slave (Debug Port:0XB4,ISP:0X98)
CHIP_CONF:{DIM2,DIM1,DIM0}
CHIP_CONF=3'd7:111:boot from SPI Flash
+3.3V_NORMAL
OPT
10K
10K
R1908
R1902
10K
OPT
R1907
10K
R1991
OPT
10K
R1906
10K
R1990
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
URSA Reset
+3.3V_NORMAL
SW1901
+3.3V_NORMAL
JTP-1127WEM
OPT
1
2
C1996
22uF
R1919
3
4
10V
10K
URSA9_RST_PULLUP
0
R1924
0
R1930
0
R13221
URSA_RESET_MICOM
IC1901-*1
W25Q32BVSSIG
/CS
VCC
1
8
DO[IO1]
/HOLD[IO3]
2
7
/WP[IO2]
CLK
3
6
+3.3V_NORMAL
GND
DI[IO0]
4
5
IC1901
SPI_4MB_Winbond
VCC
C1995
1
8
0.1uF
16V
SPI_4MB_MACRONIX
HOLD#
2
7
10K
R1903
SCLK
3
6
SPI_CK_URSA9
SI/SIO0
4
5
SPI_DI_URSA9
Debugging for URSA9
I2C_S Port
P1905
12507WS-04L
WAFER-STRAIGHT
URSA_DEBUG
DIM0
1
2
I2C_SCL4
DIM1
R1922
33
3
SCL2_+3.3V_DB
URSA_DEBUG
I2CS_SCL
R1921
33
4
SDA2_+3.3V_DB
URSA_DEBUG
SCL2_+3.3V_DB
DIM2
5
URSA_RESET
URSA_RESET_SoC
URSA_RESET_MICOM
+3.3V_NORMAL
URSA_RESET
URSA9_PQ_DEBUG
P1906
XIN_URSA
12507WS-04L
XO_URSA
1
I2CS_SDA
AR13201
R13222
33
I2CS_SCL
C1990
2
C1991
47pF
47pF
URSA9_PQ_DEBUG
50V
50V
OPT
OPT
3
R13223
33
4
URSA9_PQ_DEBUG
5
C1998
0.1uF
16V
URSA9_PQ_DEBUG
+3.3V_NORMAL
R13225
URSA9_SYS_DEBUG
33
P1907
Change pin from A5 to C4
URSA9_SYS_DEBUG
12507WS-04L
+3.3V_NORMAL
SPI_CZ_URSA9
1
SPI_CK_URSA9
AR13200
1K
SPI_DI_URSA9
2
R1954
SPI_DO_URSA9
3
OPT
33
R1981
4
OPT
33
R1933
TCON_I2C_EN Ready
10K
URSA9_SYS_DEBUG
5
C1997
R1955
0.1uF
16V
R13224
33
URSA9_SYS_DEBUG
SW1902
JS2235S
1
6
I2C_SDA4
R1958
R1959
0
0
URSA_MP
URSA_MP
2
5
I2CS_SDA
R1960
R1961
URSA_DEBUG_SW
0
0
OPT
OPT
3
4
SDA2_+3.3V_DB
URSA9 Option
BIT [1/0]
Module Division
URSA_OPT_5
0/0
Non Division
URSA_OPT_6
0/1
2 Division
Div_BIT0
1/0
4 Division
Div_BIT1
1/1
8 Division
URSA_OPT_4
URSA_OPT_0
URSA_OPT_1
BIT [2/1/0]
Tx Lane
URSA_BIT0
0/0/0
4K@120 (16lane)
URSA_BIT1
0/0/1
4k@60 (8lane)
URSA_BIT2
0/1/0
5k@120 (20lane)
0/1/1
OLED ULTRA HD
1/0/0
FHD@120 (4lane)
1/0/1
FHD@60 (2lane)
1/1/0
Reserved
1/1/1
Reserved
IC2500
LGE7411(URSA9)
AF29
RESET
I2C_HSC_SDA/VSYNC_LIKE2
I2C_HSC_SCL/VSYNC_LIKE3
R3
XTALO
R4
XTALI
SPI1_CK/PWM2/GPIO58
SPI1_DI/PWM3/GPIO59
AJ24
I2CS_SDA
SPI2_CK/PWM0/GPIO56
AH24
33
I2CS_SCL
SPI2_DI/PWM1/GPIO57
SPI3_CK/DIM10/GPIO54
AH26
I2CM_SDA
SPI3_DI/DIM11/GPIO55
AG24
I2CM_SCL/VSYNC_LIKE1
SPI4_CK/DIM8/GPIO52
SPI4_DI/DIM9/GPIO53
B4
GPIO[0][UART2_TX]
A4
GPIO[1][UART2_RX]
VSYNC_LIKE/PWM5/GPIO40
B5
GPIO[2][UART1_TX]
A5
GPIO[3][UART1_RX]
DIM0/GPIO[32]
DIM1/GPIO[33]
DIM2/GPIO[34]
AD28
SPI_CZ
DIM3/GPIO[35]
AD30
SPI_CK
DIM4/GPIO[36]
AC31
33
SPI_DI
DIM5/GPIO[37]
AD29
SPI_DO
DIM6/GPIO[38]
DIM7/GPIO[39]
AE28
INT_R21/GPIO[41]
AE27
INT_R20/GPIO[42]
GPIO43/TCON0
GPIO44/TCON1
GPIO45/TCON2
C4
IRE
GPIO46/TCON3
GPIO47/TCON4
URSA9 UART1_RX
GPIO48/TCON5
GPIO49/TCON6
AC27
GND_1
GPIO50/TCON7
AD27
GND_2
GPIO[18]/TCON8
A7
NC_1
GPIO[19]/TCON9
B6
NC_2
GPIO[20]/TCON10
B7
NC_3
GPIO[21]/TCON11
C5
NC_4
GPIO[22]/TCON12
C6
NC_5
GPIO[23]/TCON13
C7
NC_6
GPIO24/TCON14
D4
NC_7
GPIO25/TCON15
D5
NC_8
D6
NC_9
GPIO[4]
D7
NC_10
GPIO[5]
E4
NC_11
GPIO[6]
E5
NC_12
GPIO[7]
E6
NC_13
GPIO[8]
E7
NC_14
GPIO[9]
F4
NC_15
GPIO[10]/PWM_DIM_IN[0]
F5
NC_16
GPIO[11]/PWM_DIM_IN[1]
M5
NC_17
GPIO[12]
M6
NC_18
GPIO[13]
M7
NC_19
GPIO[14]
N5
NC_20
GPIO[15]
R7
NC_21
GPIO[16]
P7
NC_22
GPIO[17]
N7
NC_23
N6
NC_24
+3.3V_NORMAL
Division Type
Module Type
Rx Interface
Tx Lane
AG25
AH25
AH28
URSA_OPT_0
Module Division OPT
AJ27
Div_BIT0
AJ29
Div_BIT1
+3.3V_NORMAL
AF27
URSA_OPT_4
AG28
OPT
URSA_OPT_5
R1936
AH27
10K
URSA_OPT_6
AG27
33
R1935
3D_EN
R1934 33
AG26
L_DIM_EN
R1937
10K
OPT
OPT
AF28
R13203
33
AG23
+3.3V_NORMAL
DIM0
AG20
DIM1
OPT
AH23
R13204
DIM2
10K
AH20
AG21
URSA_OPT_1
R13205
AH22
10K
URSA_BIT0
AG22
URSA_BIT1
AH21
URSA_BIT2
A3
B3
A2
C3
B2
B1
C2
C1
AG4
AG5
HDMI OUTPUT_SIL9617 DDC to URSA9_1
AH4
AH5
AH6
AJ4
AJ5
AJ6
AH16
R13210
0
Data_Format_1
AG16
R13211
0
HDMI OUTPUT_R9531AN DDC to URSA9_0
Data_Format_0
Y5
RXBSCL_URSA9
Y4
RXBSDA_URSA9
AB4
AB5
For DFT JIG
OPT
AG17
R13207
33
R13206
R13209
100K
100K
OPT
AH17
R13208
33
AG18
10K
R13201
URSA_RX_Vx1_HTPDn
AJ20
R13200
10K
URSA_RX_Vx1_HTPDn
AH18
URSA9_Vx1_RX_HTPD_GPIO
URSA9_CONNECT
AG19
LOCKAn_OSD
AH19
LOCKAn_Video
AJ21
FLASH_WP_URSA
BSD-14Y-UD-132-HD
2013.12.17
LGE Internal Use Only
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