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H5TQ4G63AFR-RDC
N3
M0_DDR_A0
P7
M0_DDR_A1
P3
M0_DDR_A2
N2
M0_DDR_A3
P8
M0_DDR_A4
P2
M0_DDR_A5
R8
M0_DDR_A6
R2
M0_DDR_A7
T8
M0_DDR_A8
R3
M0_DDR_A9
L7
M0_DDR_A10
R7
M0_DDR_A11
N7
M0_DDR_A12
T3
M0_DDR_A13
T7
M0_DDR_A14
M7
M0_DDR_A15
M2
M0_DDR_BA0
N8
M0_DDR_BA1
M3
M0_DDR_BA2
J7
M0_D_CLK
K7
M0_D_CLKN
K9
M0_DDR_CKE
L2
M0_DDR_CS1
K1
M0_DDR_ODT
J3
M0_DDR_RASN
K3
M0_DDR_CASN
L3
M0_DDR_WEN
T2
M0_DDR_RESET_N
F3
M0_DDR_DQS0
G3
M0_DDR_DQS_N0
C7
M0_DDR_DQS1
B7
M0_DDR_DQS_N1
E7
M0_DDR_DM0
D3
M0_DDR_DM1
E3
M0_DDR_DQ0
F7
M0_DDR_DQ1
F2
M0_DDR_DQ2
F8
M0_DDR_DQ3
H3
M0_DDR_DQ4
H8
M0_DDR_DQ5
G2
M0_DDR_DQ6
H7
M0_DDR_DQ7
D7
M0_DDR_DQ8
C3
M0_DDR_DQ9
C8
M0_DDR_DQ10
C2
M0_DDR_DQ11
A7
M0_DDR_DQ12
A2
M0_DDR_DQ13
B8
M0_DDR_DQ14
A3
M0_DDR_DQ15
+1.5V_Bypass Cap
Close to DDR Power Pin
VDDC15_M0
F16
M0_DDR_A0
A_DDR3_A0
C16
M0_DDR_A1
A_DDR3_A1
E16
M0_DDR_A2
A_DDR3_A2
F17
M0_DDR_A3
A_DDR3_A3
B17
M0_DDR_A4
A_DDR3_A4
E17
M0_DDR_A5
A_DDR3_A5
A16
M0_DDR_A6
A_DDR3_A6
D16
M0_DDR_A7
A_DDR3_A7
C15
M0_DDR_A8
A_DDR3_A8
E15
M0_DDR_A9
A_DDR3_A9
B18
M0_DDR_A10
A_DDR3_A10
B16
M0_DDR_A11
A_DDR3_A11
D19
M0_DDR_A12
A_DDR3_A12
F15
M0_DDR_A13
A_DDR3_A13
B15
M0_DDR_A14
A_DDR3_A14
E19
M0_DDR_A15
A_DDR3_A15
E18
M0_DDR_BA0
A_DDR3_BA0
C17
M0_DDR_BA1
A_DDR3_BA1
F18
M0_DDR_BA2
A_DDR3_BA2
F20
M0_DDR_RASN
A_DDR3_RASZ
F19
M0_DDR_CASN
A_DDR3_CASZ
E20
M0_DDR_WEN
A_DDR3_WEZ
G21
M0_DDR_ODT
A_DDR3_ODT
C18
M0_DDR_CKE
A_DDR3_CKE
F14
M0_DDR_RESET_N
A_DDR3_RST
A19
M0_D_CLK
A_DDR3_MCLK
B19
M0_D_CLKN
A_DDR3_MCLKZ
E14
M0_DDR_CS1
A_DDR3_CSB1
D14
M0_DDR_CS2
A_DDR3_CSB2
C22
M0_DDR_DQ0
A_DDR3_DQ[0]
B21
M0_DDR_DQ1
A_DDR3_DQ[1]
B23
M0_DDR_DQ2
A_DDR3_DQ[2]
C20
M0_DDR_DQ3
A_DDR3_DQ[3]
B24
M0_DDR_DQ4
A_DDR3_DQ[4]
C19
M0_DDR_DQ5
A_DDR3_DQ[5]
C23
M0_DDR_DQ6
A_DDR3_DQ[6]
C21
M0_DDR_DQ7
A_DDR3_DQ[7]
B20
M0_DDR_DM0
A_DDR3_DQM[0]
A22
M0_DDR_DQS0
A_DDR3_DQS[0]
B22
M0_DDR_DQS_N0
A_DDR3_DQSB[0]
F22
M0_DDR_DQ8
A_DDR3_DQ[8]
E24
M0_DDR_DQ9
A_DDR3_DQ[9]
E21
M0_DDR_DQ10
A_DDR3_DQ[10]
E25
M0_DDR_DQ11
A_DDR3_DQ[11]
D22
M0_DDR_DQ12
A_DDR3_DQ[12]
D26
M0_DDR_DQ13
A_DDR3_DQ[13]
D21
M0_DDR_DQ14
A_DDR3_DQ[14]
D25
M0_DDR_DQ15
A_DDR3_DQ[15]
E23
M0_DDR_DM1
A_DDR3_DQM[1]
D23
M0_DDR_DQS1
A_DDR3_DQS[1]
E22
M0_DDR_DQS_N1
A_DDR3_DQSB[1]
C27
M0_DDR_DQ16
A_DDR3_DQ[16]
C25
M0_DDR_DQ17
A_DDR3_DQ[17]
B28
M0_DDR_DQ18
A_DDR3_DQ[18]
A25
M0_DDR_DQ19
A_DDR3_DQ[19]
C28
M0_DDR_DQ20
A_DDR3_DQ[20]
C24
M0_DDR_DQ21
A_DDR3_DQ[21]
A28
M0_DDR_DQ22
A_DDR3_DQ[22]
B26
M0_DDR_DQ23
A_DDR3_DQ[23]
B25
M0_DDR_DM2
A_DDR3_DQM[2]
B27
M0_DDR_DQS2
A_DDR3_DQS[2]
C26
M0_DDR_DQS_N2
A_DDR3_DQSB[2]
D28
M0_DDR_DQ24
A_DDR3_DQ[24]
C29
M0_DDR_DQ25
A_DDR3_DQ[25]
E26
M0_DDR_DQ26
A_DDR3_DQ[26]
D29
M0_DDR_DQ27
A_DDR3_DQ[27]
E28
M0_DDR_DQ28
A_DDR3_DQ[28]
D30
M0_DDR_DQ29
A_DDR3_DQ[29]
E27
M0_DDR_DQ30
A_DDR3_DQ[30]
C30
M0_DDR_DQ31
A_DDR3_DQ[31]
B30
M0_DDR_DM3
A_DDR3_DQM[3]
A30
M0_DDR_DQS3
A_DDR3_DQS[3]
B29
M0_DDR_DQS_N3
A_DDR3_DQSB[3]
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
Copyright © 2014 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
M0_DDR_VREFDQ
IC400
EAN63053201
DDR3
M8
M0_DDR_A0
A0
VREFCA
4Gbit
M0_DDR_A1
A1
(x16)
M0_DDR_A2
A2
H1
M0_DDR_A3
A3
VREFDQ
M0_DDR_A4
A4
M0_DDR_A5
A5
L8
R400
240
A6
ZQ
M0_DDR_A6
VDDC15_M0
M0_DDR_A7
A7
M0_DDR_A8
A8
B2
M0_DDR_A9
A9
VDD_1
D9
M0_DDR_A10
A10/AP
VDD_2
G7
M0_DDR_A11
A11
VDD_3
K2
M0_DDR_A12
A12/BC
VDD_4
K8
M0_DDR_A13
A13
VDD_5
N1
M0_DDR_A14
A14
VDD_6
N9
M0_DDR_A15
NC_5
VDD_7
R1
VDD_8
R9
M0_DDR_BA0
BA0
VDD_9
M0_DDR_BA1
BA1
BA2
M0_DDR_BA2
A1
VDDQ_1
A8
M0_D_CLK
CK
VDDQ_2
C1
M0_D_CLKN
CK
VDDQ_3
C9
M0_DDR_CKE
CKE
VDDQ_4
D2
VDDQ_5
E9
M0_DDR_CS2
CS
VDDQ_6
F1
M0_DDR_ODT
ODT
VDDQ_7
H2
C410
0.1uF
M0_DDR_RASN
RAS
VDDQ_8
H9
C411
0.1uF
M0_DDR_CASN
CAS
VDDQ_9
M0_DDR_WEN
WE
J1
NC_1
J9
M0_DDR_RESET_N
RESET
NC_2
L1
NC_3
L9
NC_4
M0_DDR_DQS2
DQSL
M0_DDR_DQS_N2
DQSL
A9
M0_DDR_DQS3
DQSU
VSS_1
B3
M0_DDR_DQS_N3
DQSU
VSS_2
E1
VSS_3
G8
M0_DDR_DM2
DML
VSS_4
J2
M0_DDR_DM3
DMU
VSS_5
J8
VSS_6
M1
M0_DDR_DQ16
DQL0
VSS_7
M9
M0_DDR_DQ17
DQL1
VSS_8
P1
DQL2
VSS_9
M0_DDR_DQ18
P9
M0_DDR_DQ19
DQL3
VSS_10
T1
M0_DDR_DQ20
DQL4
VSS_11
T9
M0_DDR_DQ21
DQL5
VSS_12
M0_DDR_DQ22
DQL6
M0_DDR_DQ23
DQL7
B1
VSSQ_1
B9
M0_DDR_DQ24
DQU0
VSSQ_2
D1
M0_DDR_DQ25
DQU1
VSSQ_3
D8
M0_DDR_DQ26
DQU2
VSSQ_4
E2
M0_DDR_DQ27
DQU3
VSSQ_5
E8
M0_DDR_DQ28
DQU4
VSSQ_6
F9
M0_DDR_DQ29
DQU5
VSSQ_7
G1
DQU6
VSSQ_8
M0_DDR_DQ30
G9
M0_DDR_DQ31
DQU7
VSSQ_9
+1.5V_Bypass Cap
Close to DDR Power Pin
VDDC15_M0
OPT
OPT
OPT
C4000
C4004
C4011
10uF
1uF
0.1uF
10V
4th layer
25V
16V
IC100
LGE4331
G28
B_DDR3_A0
M1_DDR_A0
M0_DDR_A14
J31
B_DDR3_A1
M1_DDR_A1
M0_DDR_A8
H29
B_DDR3_A2
M1_DDR_A2
M0_DDR_A11
J27
B_DDR3_A3
M1_DDR_A3
M0_DDR_A6
J30
M1_DDR_A4
B_DDR3_A4
H28
M1_DDR_A5
B_DDR3_A5
J32
B_DDR3_A6
M1_DDR_A6
G31
M0_DDR_A1
B_DDR3_A7
M1_DDR_A7
H32
M0_DDR_A4
B_DDR3_A8
M1_DDR_A8
F30
M0_DDR_A12
B_DDR3_A9
M1_DDR_A9
K30
M0_DDR_BA1
B_DDR3_A10
M1_DDR_A10
H30
M1_DDR_A11
B_DDR3_A11
K29
B_DDR3_A12
M1_DDR_A12
F31
B_DDR3_A13
M1_DDR_A13
H31
M0_DDR_RESET_N
B_DDR3_A14
M1_DDR_A14
L28
M0_DDR_A13
B_DDR3_A15
M1_DDR_A15
K28
M0_DDR_A7
B_DDR3_BA0
M1_DDR_BA0
K31
M0_DDR_A9
M1_DDR_BA1
B_DDR3_BA1
J28
M1_DDR_BA2
B_DDR3_BA2
M27
B_DDR3_RASZ
M1_DDR_RASN
L27
B_DDR3_CASZ
M1_DDR_CASN
K27
M0_DDR_A5
B_DDR3_WEZ
M1_DDR_WEN
M0_DDR_A2
M28
B_DDR3_ODT
M1_DDR_ODT
M0_DDR_A3
L31
B_DDR3_CKE
M1_DDR_CKE
M0_DDR_A0
F32
M1_DDR_RESET_N
B_DDR3_RST
M32
B_DDR3_MCLK
M1_D_CLK
L30
B_DDR3_MCLKZ
M1_D_CLKN
F29
B_DDR3_CSB1
M1_DDR_CS1
M0_DDR_BA0
E32
B_DDR3_CSB2
M1_DDR_CS2
M0_DDR_BA2
M0_DDR_A15
M0_DDR_A10
R31
M1_DDR_DQ0
B_DDR3_DQ[0]
N30
M1_DDR_DQ1
B_DDR3_DQ[1]
R30
B_DDR3_DQ[2]
M1_DDR_DQ2
N31
M0_DDR_WEN
B_DDR3_DQ[3]
M1_DDR_DQ3
T30
M0_DDR_CASN
B_DDR3_DQ[4]
M1_DDR_DQ4
M31
M0_DDR_RASN
B_DDR3_DQ[5]
M1_DDR_DQ5
T31
M1_DDR_DQ6
M0_DDR_ODT
B_DDR3_DQ[6]
P31
M1_DDR_DQ7
B_DDR3_DQ[7]
M30
B_DDR3_DQM[0]
M1_DDR_DM0
R32
B_DDR3_DQS[0]
M1_DDR_DQS0
P30
M0_DDR_CKE
B_DDR3_DQSB[0]
M1_DDR_DQS_N0
M0_D_CLKN
P28
M0_D_CLK
M1_DDR_DQ8
B_DDR3_DQ[8]
T28
M1_DDR_DQ9
B_DDR3_DQ[9]
N28
B_DDR3_DQ[10]
M1_DDR_DQ10
U28
B_DDR3_DQ[11]
M1_DDR_DQ11
N27
B_DDR3_DQ[12]
M1_DDR_DQ12
T27
B_DDR3_DQ[13]
M1_DDR_DQ13
N29
M1_DDR_DQ14
B_DDR3_DQ[14]
T29
M1_DDR_DQ15
B_DDR3_DQ[15]
R28
B_DDR3_DQM[1]
M1_DDR_DM1
R27
B_DDR3_DQS[1]
M1_DDR_DQS1
P27
B_DDR3_DQSB[1]
M1_DDR_DQS_N1
Y31
M1_DDR_DQ16
B_DDR3_DQ[16]
V31
M1_DDR_DQ17
B_DDR3_DQ[17]
Y30
B_DDR3_DQ[18]
M1_DDR_DQ18
V32
B_DDR3_DQ[19]
M1_DDR_DQ19
AA30
B_DDR3_DQ[20]
M1_DDR_DQ20
U31
B_DDR3_DQ[21]
M1_DDR_DQ21
AA31
M1_DDR_DQ22
B_DDR3_DQ[22]
V30
M1_DDR_DQ23
B_DDR3_DQ[23]
U30
B_DDR3_DQM[2]
M1_DDR_DM2
W30
B_DDR3_DQS[2]
M1_DDR_DQS2
W31
B_DDR3_DQSB[2]
M1_DDR_DQS_N2
V28
M1_DDR_DQ24
B_DDR3_DQ[24]
Y27
M1_DDR_DQ25
B_DDR3_DQ[25]
U27
B_DDR3_DQ[26]
M1_DDR_DQ26
AA28
B_DDR3_DQ[27]
M1_DDR_DQ27
W28
B_DDR3_DQ[28]
M1_DDR_DQ28
AA29
B_DDR3_DQ[29]
M1_DDR_DQ29
V27
M1_DDR_DQ30
B_DDR3_DQ[30]
AA27
M1_DDR_DQ31
B_DDR3_DQ[31]
W27
B_DDR3_DQM[3]
M1_DDR_DM3
Y28
B_DDR3_DQS[3]
M1_DDR_DQS3
W29
B_DDR3_DQSB[3]
M1_DDR_DQS_N3
M0_1_DDR_VREFDQ
IC401
H5TQ4G63AFR-RDC
H5TQ4G63AFR-RDC
EAN63053201
N3
DDR3
M8
N3
A0
VREFCA
M1_DDR_A0
P7
4Gbit
A0
P7
A1
P3
M1_DDR_A1
A1
(x16)
P3
A2
M1_DDR_A2
A2
N2
H1
N2
A3
VREFDQ
M1_DDR_A3
A3
P8
P8
A4
M1_DDR_A4
A4
P2
P2
A5
M1_DDR_A5
A5
R8
L8
R403
240
R8
A6
ZQ
M1_DDR_A6
R2
A6
R2
A7
VDDC15_M0
M1_DDR_A7
T8
A7
T8
A8
R3
B2
M1_DDR_A8
A8
R3
A9
VDD_1
M1_DDR_A9
A9
L7
D9
L7
A10/AP
VDD_2
M1_DDR_A10
A10/AP
R7
G7
R7
A11
VDD_3
M1_DDR_A11
A11
N7
K2
N7
A12/BC
VDD_4
M1_DDR_A12
A12/BC
T3
K8
T3
A13
VDD_5
M1_DDR_A13
T7
N1
A13
T7
A14
VDD_6
M7
N9
M1_DDR_A14
A14
M7
NC_5
VDD_7
M1_DDR_A15
NC_5
R1
VDD_8
M2
R9
M2
BA0
VDD_9
M1_DDR_BA0
BA0
N8
N8
BA1
M1_DDR_BA1
BA1
M3
M3
BA2
M1_DDR_BA2
A1
BA2
VDDQ_1
J7
A8
J7
CK
VDDQ_2
K7
C1
M1_D_CLK
CK
K7
CK
VDDQ_3
M1_D_CLKN
CK
K9
C9
K9
CKE
VDDQ_4
M1_DDR_CKE
CKE
D2
VDDQ_5
L2
E9
L2
CS
VDDQ_6
M1_DDR_CS1
CS
K1
F1
K1
ODT
VDDQ_7
M1_DDR_ODT
J3
H2
ODT
C440
0.1uF
J3
RAS
VDDQ_8
K3
H9
M1_DDR_RASN
RAS
C441
0.1uF
K3
CAS
VDDQ_9
L3
M1_DDR_CASN
CAS
L3
WE
M1_DDR_WEN
WE
J1
NC_1
T2
J9
T2
RESET
NC_2
M1_DDR_RESET_N
RESET
L1
NC_3
L9
NC_4
F3
F3
DQSL
G3
M1_DDR_DQS0
DQSL
G3
DQSL
M1_DDR_DQS_N0
DQSL
C7
A9
C7
DQSU
VSS_1
M1_DDR_DQS1
DQSU
B7
B3
B7
DQSU
VSS_2
M1_DDR_DQS_N1
DQSU
E1
VSS_3
E7
G8
E7
DML
VSS_4
D3
J2
M1_DDR_DM0
DML
D3
DMU
VSS_5
J8
M1_DDR_DM1
DMU
VSS_6
E3
M1
E3
DQL0
VSS_7
M1_DDR_DQ0
DQL0
F7
M9
F7
DQL1
VSS_8
M1_DDR_DQ1
DQL1
F2
P1
F2
DQL2
VSS_9
M1_DDR_DQ2
F8
P9
DQL2
F8
DQL3
VSS_10
M1_DDR_DQ3
H3
T1
DQL3
H3
DQL4
VSS_11
H8
T9
M1_DDR_DQ4
DQL4
H8
DQL5
VSS_12
M1_DDR_DQ5
DQL5
G2
G2
DQL6
M1_DDR_DQ6
DQL6
H7
H7
DQL7
M1_DDR_DQ7
DQL7
B1
VSSQ_1
D7
B9
D7
DQU0
VSSQ_2
M1_DDR_DQ8
C3
D1
DQU0
C3
DQU1
VSSQ_3
C8
D8
M1_DDR_DQ9
DQU1
C8
DQU2
VSSQ_4
C2
E2
M1_DDR_DQ10
DQU2
C2
DQU3
VSSQ_5
M1_DDR_DQ11
DQU3
A7
E8
A7
DQU4
VSSQ_6
M1_DDR_DQ12
DQU4
A2
F9
A2
DQU5
VSSQ_7
M1_DDR_DQ13
DQU5
B8
G1
B8
DQU6
VSSQ_8
M1_DDR_DQ14
A3
G9
DQU6
A3
DQU7
VSSQ_9
M1_DDR_DQ15
DQU7
+1.5V_Bypass Cap
Close to DDR Power Pin
VDDC15_M0
OPT
OPT
OPT
C4001
C4005
C4010
4th layer
10uF
1uF
0.1uF
10V
25V
16V
DDR_VTT
AR400
AR407
100
100
1/16W
1/16W
C424
0.1uF
M1_DDR_A14
M1_DDR_A8
M1_DDR_A11
C425
0.1uF
M1_DDR_A6
AR401
AR408
100
100
1/16W
1/16W
C426
0.1uF
M1_DDR_A1
M1_DDR_A4
M1_DDR_A12
C427
0.1uF
M1_DDR_BA1
AR402
AR409
100
100
1/16W
1/16W
C428
0.1uF
M1_DDR_RESET_N
M1_DDR_A13
M1_DDR_A7
C429
0.1uF
M1_DDR_A9
AR403
AR410
100
100
1/16W
1/16W
C430
0.1uF
M1_DDR_A5
M1_DDR_A2
M1_DDR_A3
C431
0.1uF
M1_DDR_A0
AR404
AR411
100
100
1/16W
1/16W
C432
0.1uF
M1_DDR_BA0
M1_DDR_BA2
M1_DDR_A15
C433
0.1uF
M1_DDR_A10
AR405
AR412
100
100
1/16W
1/16W
C434
0.1uF
M1_DDR_WEN
M1_DDR_CASN
M1_DDR_RASN
C435
0.1uF
M1_DDR_ODT
AR406
AR413
100
100
1/16W
1/16W
C436
0.1uF
M1_DDR_CKE
M1_D_CLKN
C437
0.1uF
M1_D_CLK
* DDR_VTT
VDDC15_M0
+3.3V_NORMAL
R401
IC402
10K 1%
TPS51200DRCR
[EP]
L401
UBW2012-121F
R402
C421
10K
1000pF
REFIN
VIN
1%
1
10
VLDOIN
PGOOD
C443
2
9
4700pF
DDR_VTT
VO
GND
C422
3
8
22uF
10V
PGND
EN
L400
4
7
UBW2012-121F
VOSNS
REFOUT
5
6
C414
C417
C442
0.1uF
100uF
0.1uF
Close to REFOUT pin
M1_DDR_VREFDQ
IC403
EAN63053201
N3
DDR3
M8
M1_DDR_A0
VREFCA
P7
4Gbit
M1_DDR_A1
P3
(x16)
M1_DDR_A2
H1
N2
M1_DDR_A3
VREFDQ
P8
M1_DDR_A4
P2
M1_DDR_A5
R8
L8
R404
240
M1_DDR_A6
ZQ
R2
VDDC15_M0
M1_DDR_A7
T8
M1_DDR_A8
B2
R3
M1_DDR_A9
VDD_1
D9
L7
M1_DDR_A10
VDD_2
R7
G7
M1_DDR_A11
VDD_3
N7
K2
VDD_4
M1_DDR_A12
T3
K8
M1_DDR_A13
VDD_5
T7
N1
M1_DDR_A14
VDD_6
M7
N9
M1_DDR_A15
VDD_7
R1
VDD_8
R9
M2
M1_DDR_BA0
VDD_9
N8
M1_DDR_BA1
M3
M1_DDR_BA2
A1
VDDQ_1
J7
A8
M1_D_CLK
VDDQ_2
C1
K7
M1_D_CLKN
VDDQ_3
C9
K9
M1_DDR_CKE
VDDQ_4
D2
VDDQ_5
L2
E9
M1_DDR_CS2
VDDQ_6
K1
F1
M1_DDR_ODT
VDDQ_7
J3
H2
C468
0.1uF
M1_DDR_RASN
VDDQ_8
K3
H9
C469
0.1uF
M1_DDR_CASN
VDDQ_9
L3
M1_DDR_WEN
J1
NC_1
T2
J9
M1_DDR_RESET_N
NC_2
L1
NC_3
L9
NC_4
F3
M1_DDR_DQS2
G3
M1_DDR_DQS_N2
C7
A9
M1_DDR_DQS3
VSS_1
B7
B3
VSS_2
M1_DDR_DQS_N3
E1
VSS_3
E7
G8
M1_DDR_DM2
VSS_4
D3
J2
M1_DDR_DM3
VSS_5
J8
VSS_6
M1
E3
M1_DDR_DQ16
VSS_7
F7
M9
M1_DDR_DQ17
VSS_8
F2
P1
M1_DDR_DQ18
VSS_9
F8
P9
M1_DDR_DQ19
VSS_10
H3
T1
M1_DDR_DQ20
VSS_11
H8
T9
M1_DDR_DQ21
VSS_12
G2
M1_DDR_DQ22
H7
M1_DDR_DQ23
B1
VSSQ_1
D7
B9
M1_DDR_DQ24
VSSQ_2
C3
D1
M1_DDR_DQ25
VSSQ_3
C8
D8
M1_DDR_DQ26
VSSQ_4
E2
C2
M1_DDR_DQ27
VSSQ_5
E8
A7
M1_DDR_DQ28
VSSQ_6
A2
F9
M1_DDR_DQ29
VSSQ_7
B8
G1
M1_DDR_DQ30
VSSQ_8
A3
G9
M1_DDR_DQ31
VSSQ_9
+1.5V_Bypass Cap
Close to DDR Power Pin
VDDC15_M0
OPT
OPT
OPT
C4002
4th layer
C4006
C4009
10uF
1uF
0.1uF
10V
25V
16V
DDR_VTT
C453
0.1uF
C454
0.1uF
C455
0.1uF
C456
0.1uF
C457
0.1uF
C458
0.1uF
VDDC15_M0
M0_DDR_CKE
C459
0.1uF
R418
R405
10K
C460
0.1uF
10K
M0_DDR_RESET_N
C461
0.1uF
C462
0.1uF
M0_D_CLK
R412
C477
56
0.01uF
1%
50V
C463
0.1uF
R413
56
1%
C464
0.1uF
M0_D_CLKN
C465
0.1uF
C466
0.1uF
VDDC15_M0
VDDC15_M0
M0_1_DDR_VREFDQ
M0_DDR_VREFDQ
C479
C472
0.1uF
0.1uF
C474
1000pF
50V
M1_1_DDR_VREFDQ
IC404
H5TQ4G63AFR-RDC
EAN63053201
DDR3
M8
A0
VREFCA
4Gbit
A1
(x16)
A2
H1
A3
VREFDQ
A4
A5
L8
R419
240
A6
ZQ
A7
VDDC15_M0
A8
B2
A9
VDD_1
D9
A10/AP
VDD_2
G7
A11
VDD_3
K2
A12/BC
VDD_4
K8
A13
VDD_5
N1
A14
VDD_6
N9
NC_5
VDD_7
R1
VDD_8
R9
BA0
VDD_9
BA1
BA2
A1
VDDQ_1
A8
CK
VDDQ_2
C1
CK
VDDQ_3
C9
CKE
VDDQ_4
D2
VDDQ_5
E9
CS
VDDQ_6
F1
ODT
VDDQ_7
H2
C490
0.1uF
RAS
VDDQ_8
H9
C491
0.1uF
CAS
VDDQ_9
WE
J1
NC_1
J9
RESET
NC_2
L1
NC_3
L9
NC_4
DQSL
DQSL
A9
DQSU
VSS_1
B3
DQSU
VSS_2
E1
VSS_3
G8
DML
VSS_4
J2
DMU
VSS_5
J8
VSS_6
M1
DQL0
VSS_7
M9
DQL1
VSS_8
P1
DQL2
VSS_9
P9
DQL3
VSS_10
T1
DQL4
VSS_11
T9
DQL5
VSS_12
DQL6
DQL7
B1
VSSQ_1
B9
DQU0
VSSQ_2
D1
DQU1
VSSQ_3
D8
DQU2
VSSQ_4
E2
DQU3
VSSQ_5
E8
DQU4
VSSQ_6
F9
DQU5
VSSQ_7
G1
DQU6
VSSQ_8
G9
DQU7
VSSQ_9
OPT
OPT
OPT
C4003
C4007
C4008
10uF
1uF
0.1uF
4th layer
10V
25V
16V
VDDC15_M0
M1_DDR_CKE
R433
R422
10K
10K
M1_DDR_RESET_N
M1_D_CLK
R427
C497
56
0.01uF
1%
50V
R428
56
1%
M1_D_CLKN
VDDC15_M0
VDDC15_M0
M1_1_DDR_VREFDQ
M1_DDR_VREFDQ
C470
C473
0.1uF
0.1uF
C483
C478
C471
1000pF
1000pF
1000pF
50V
50V
50V
UB83
2013-10-28
LM14 DDR
04
LGE Internal Use Only
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