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Circuit Diagrams and PWB Layouts
SSB: Feature Box
FEATURE BOX
7300
BACK END PROCESSING
Y
Y
COMPENSATION
DELAY
PANORAMA
U
UV
DCTI
V
CONTROL INTERFACE
PI-DTL MMIO ADAPTER
7300
MEMORY BASED PROCESSING
SUB
CHANNEL
HORIZONTAL
VERTICAL
YUV
COMPRESSION
COMPRESSION
SUB
FIFO CACHE
MAIN
CHANNEL
MAIN
HORIZONTAL
YUV
COMPRESSION
FIFO CACHE
CONTROL INTERFACE
DTL MMIO
MMIO ADAPTER
PI-BUS
3139 123 5536.2
ES1E AA
7.
LUMINANCE SHARPNESS
256
SHARPNESS
MEASURE
FILTERS
LTI
Y
Y
DYNAMIC
PEAKING
U
U
COMPENSATION
V
V
DELAY
NOISE
SHAPE
DTL INTERFACE
UNDITHER
MEMORY BUS
DEVICE
INTERFACE
UNDITHER
NOISE
DNR
SHAPE
UNDITHER
MODE CONTROL
DISPLAY CONTROLLER
42
COLOUR FEATURES
Y
R
COLOUR
SKIN
BLUE
GREEN
U
G
TONE
SPACE
STRETCH
ENHANCE
V
B
CONTROL
CONVERSION
SDRAM
FRONT END PROCESSING
VIA
MMI
YUV
FROM
VIDDEC2
SCAN RATE
YUV
CONVERSION
FROM
VIDDEC1
OUTPUT
TO BEF
YUV
MULTIPLEXER
MEMORY BASED FEATURES
R
FRAME
G
PROCESSING
B
7300
SAMPLE RATE
BLACK
CONVERTER
STRETCH
SAMPLE RATE
BLACK
INPUT
CONVERTER
STRETCH
SWITCH
MATRIX
HISTOGRAM
MEASURE
Y
BLACKLEVEL
DETECTION
CONTROL INTERFACE
PI-DTL MMIO ADAPTER
YUV
SUB CHANNEL
TO MBF
HISTOGRAM
YUV
MODIFY
MAIN CHANNEL
TO MBF
MEASUREMENT BLOCKS
Y
BLACKBAR
DETECTION
NOISE
MEASURE
CL 36532058_027.eps
020903
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