Hd6417709Shf200Bv (X2687B00) Cpu(Sh3) - Yamaha TYROS 2 Service Manual

Tyros2
HD6417709SHF200BV (X2687B00) CPU (SH3)
PIN
NAME I/O
NO.
1 MD1 I
2 MD2 I
3 Vcc(RTC) -
4 XTAL2 O
5 EXTAL2 I
6 Vss(RTC) -
7 NMI I
8 IRQ0/IRL0/PTH0 I
9 IRQ1/IRL1/PTH1 I
10 IRQ2/IRL2/PTH2 I
11 IRQ3/IRL3/PTH3 I
12 IRQ4/PTH4 I
13 D31/PTB7 I/O
14 D30/PTB6 I/O
15 D29/PTB5 I/O
16 D28/PTB4 I/O
17 D27/PTB3 I/O
18 D26/PTB2 I/O
19 VssQ -
20 D25/PTB1 I/O
21 VccQ -
22 D24/PTB0 I/O
23 D23/PTA7 I/O
24 D22/PTA6 I/O
25 D21/PTA5 I/O
26 D20/PTA4 I/O
27 Vss -
28 D19/PTA3 I/O
29 Vcc -
30 D18/PTA2 I/O
31 D17/PTA1 I/O
32 D16/PTA0 I/O
33 VssQ -
34 D15 I/O
35 VccQ -
36 D14 I/O
37 D13 I/O
38 D12 I/O
39 D11 I/O
40 D10 I/O
41 D9 I/O
42 D8 I/O
43 D7 I/O
44 D6 I/O
45 VssQ -
46 D5 I/O
47 VccQ -
48 D4 I/O
49 D3 I/O
50 D2 I/O
51 D1 I/O
52 D0 I/O
53 A0 O
54 A1 O
55 A2 O
56 A3 O
57 VssQ -
58 A4 O
59 VccQ -
60 A5 O
61 A6 O
62 A7 O
63 A8 O
64 A9 O
65 A10 O
66 A11 O
67 A12 O
68 A13 O
69 VssQ -
70 A14 O
71 VccQ -
72 A15 O
73 A16 O
74 A17 O
75 A18 O
76 A19 O
77 A20 O
78 A21 O
79 Vss -
80 A22 O
81 Vcc -
82 A23 O
83 VssQ -
84 A24 O
85 VccQ -
86 A25 O
87 BS/PTK4 I/O
88 RD O
89 WE0/DQMLL O
90 WE1/DQMLU/WE O
91 I/O
WE2/DQMUL/ICIORD/PTK6
92 I/O
WE3/DQMUU/ISIOWR/PTK7
93 RD/WR O
94 AUDSYNC/PTE7 I/O
95 VssQ -
96 CS0/MCS0 O
97 VccQ -
98 CS2/PTK0 I/O
99 CS3/PTK1 I/O
100 CS4/PTK2 I/O
101 CS5/CE1A/PTK3 I/O
102 CS6/CE1B O
103 CE2A/PTE4 I/O
104 CE2B/PTE5 I/O
28
FUNCTION
Mode control
Power supply +2.0 V
Crystal oscillator
Ground
Non-maskable interrupt request
Interrupt request / Port H
Data bus / Port B
Ground
Data bus / Port B
Power supply +3.3 V
Data bus / Port B
Data bus / Port A
Ground
Data bus / Port A
Power supply +1.8 V
Data bus / Port A
Ground
Data bus
Power supply +3.3 V
Data bus
Ground
Data bus
Power supply +3.3 V
Data bus
Address bus
Ground
Address bus
Power supply +3.3 V
Address bus
Ground
Address bus
Power supply +3.3 V
Address bus
Ground
Address bus
Power supply +2.0 V
Address bus
Ground
Address bus
Power supply +3.3 V
Address bus
Bus cycle / Port K
Read strobe
Select signal (D7-D0) / D QM (SDRAM)
Select signal (D15-D8) / D QM (SDRAM) / Write enable
Select signal (D23-D16) / D QM (SDRAM) / I/O read / Port K
Select signal (D31-D24) / D QM (SDRAM) / I/O write / Port K
Read / Write
AUD cycle / Port E
Ground
Chip select / Mask ROM chip select
Power supply +3.3V
Chip select / Port K
Chip select / Chip enable / Port K
Chip select / Chip enable
Chip enable / Port E
PIN
NAME I/O
NO.
105 CKE/PTK5 I/O CK enable / Port K
106 RAS3L/PTJ0 I/O RAS address bus / Port J
107 PTJ1 I/O Port J
108 CASL/PTJ2 I/O CAS address bus / Port J
109 VssQ - Ground
110 CASU/PTJ3 I/O CAS address bus / Port J
111 VccQ - Power supply +3.3 V
112 PTJ4 I/O
Port J
113 PTJ5 I/O
114 DACK0/PTD5 I/O
DMA acknowledge / Port D
115 DACK1/PTD7 I/O
116 PTE6 I/O
Port E
117 PTE3 I/O
118 RAS3U/PTE2 I/O RAS address bus / Port E
119 PTE1 I/O Port E
120 TDO/PTE0 I/O Test data / Port E
121 BACK O Bus acknowledge
122 BREQ I Bus request
123 WAIT I Hardware wait request
124 RESETM I Manual reset
125 ADTRG/PTH5 I Analog trigger / Port H
126 IOIS16/PTG7 I Write protect / Port G
127 ASEMD0/PTG6 I ASE mode / Port G
128 ASEBRKAK/PTG5 I/O ASE break acknowledge / Port G
129 PTG4/CKIO2 I/O Port G / Clock output
130 AUDATA3/PTG3 I/O
AUD data / Port G
131 AUDATA2/PTG2 I/O
132 Vss - Ground
133 AUDATA1/PTG1 I/O AUD data / Port G
134 Vcc - Power supply +2.0 V
135 AUDATA0/PTG0 I/O AUD data / Port G
136 TRST/PTF7/PINT15 I Test reset / Port F / Port interruption
137 TMS/PTF6/PINT14 I Test mode switch / Port F / Port interruption
138 TDI/PTF5/PINT13 I Test data / Port F / Port interruption
139 TCK/PTF4/PINT12 I Test clock / Port F / Port interruption
140 IRLS3/PTF3/PINT11 I
141 IRL2/PTF2/PINT10 I
Interrupt request / Port F / Port interruption
142 IRLS1/PTF1/PINT9 I
143 IRLS0/PTF0/PINT8 I
144 MD0 I Mode control
145 Vcc(PLL1) - Power supply +2.0 V
146 CAP1 - Capacitor
147 Vss(PLL1) - Ground
148 Vss(PLL2) - Ground
149 CAP2 - Capacitor
150 VCC(PLL2) - Power supply +2.0 V
151 AUDCK/PTH6 I AUD clock / Port H
152 Vss -
Ground
153 Vss -
154 Vcc - Power supply +2.0 V
155 XTAL O
Crystal oscillator
156 EXTAL I
157 STATUS0/PTJ6 I/O
Processor status / Port J
158 STATUS1/PTJ7 I/O
159 TCLK/PTH7 I/O Timer clock / Port H
160 /IRQOUT O Interrupt request output
161 VssQ - Ground
162 CKIO I/O System clock input / output
163 VccQ - Power supply +3.3 V
164 TXD0/SCPT0 O Data transmission / SCI port
165 SCK0/SCPT1 I/O Serial clock / SCI port
166 TXD1/SCPT2 O Data transmission / SCI port
167 SCK1/SCPT3 I/O Serial clock / SCI port
168 TXD2/SCPT4 O Data transmission / SCI port
169 SCK2/SCPT5 I/O Serial clock / SCI port
170 RTS2/SCPT6 I/O Transmit request / SCI port
171 RXD0/SCPT0 I
Data reception / SCI port
172 RXD1/SCPT2 I
173 Vss - Ground
174 RXD2/SCPT4 I Data reception / SCI port
175 Vcc - Power supply +2.0 V
176 CTS2/IRQ5/SCPT7 I Transmit clear / Interrupt request / SCI port
177 MCS7/PTC7/PINT7 I/O
178 MCS6/PTC6/PINT6 I/O
Mask ROM chip select / Port C / Port interruption
179 MCS5/PTC5/PINT5 I/O
180 I/O
MCS4/PTC4/PINT4
181 - Ground
VssQ
182 I/O Standby mode Interrupt request output / Port D
WAKEUP/PTD3
183 - Power supply +3.3 V
VccQ
184 I/O Reset output / Port D
RESETOUT/PTD2
185 MCS3/PTC3/PINT3 I/O
186 MCS2/PTC2/PINT2 I/O
Mask ROM chip select / Port C / Port interruption
187 MCS1/PTC1/PINT1 I/O
MCS0/PTC0/PINT0
188 I/O
189 DRAK0/PTD1 I/O
DMA acknowledge / Port D
190 DRAK1/PTD0 I/O
191 DREQ0/PTD4 I
DMA request / Port D
192 DREQ1/PTD6 I
193 RESETP I Power on reset
194 CA I Chip active
195 MD3 I
196 MD4 I Mode control
197 MD5 I
198 AVss - Analog ground
199 AN0/PTL0 I
200 AN1/PTL1 I
201 AN2/PTL2 I
Analog input / Port L
202 AN3/PTL3 I
203 AN4/PTL4 I
204 AN5/PTL5 I
205 AVcc - Analog power supply +3.3 V
206 AN6/DA1/PTL6 I/O
Analog input / Analog output / Port L
207 AN7/DA0/PTL7 I/O
208 AVss - Analog ground
DM: IC407
FUNCTION
MO
TR
OWNE
BEDIE
MODE